another linear LOL

[n1ps]

I have been messing around with a 4 FET linear using IRFP260 power switching fets.  Attached is the spice circuit.  Hopefully it is legible and it actually attached.  In this layout I wanted to try out a "current drive" as per Floyd WA2WVL posts on the Class E forum.  I liked the idea.  So I tried it with the input of this 75M linear.  I had previously used more of a conventional binocular input, which did work, but I struggled to keep noise out of the gate circuits. 

This is a mobile amp.  I do not show the LP filter on the output.  Don't get too worked up about the DC supply .

So, if you have not fallen asleep yet, I wired up the current drive input as shown.  Same output layout as before.  In spice world, it works.  Good output.  Gate drive, not perfect, but okay.  Then to the bench....hooked it up...and....(drum roll here)...abject failure.  Both sides of the P-P amp are dead.  Good drive and no output.  So I thought I had one of the phases wrong.  But triple checks....it matches spice.  Now you may notice that in this case the input turns ratio is only 2 to 1.  I wanted to start there.  I did not push the bias any further (yet) than 2 volts.

Next up is to try it at 3-1 and maybe a little more bias.  But pretty surprised I got zilch with the 2-1. Of course it could be a stupid wiring error .    I'll see what I can do to load a picture.  But lets start here.

Peter 

[W3RSW]

Interesting topology. I can't read all your schematic values but you simply may not have enough drive through four series connected inputs .  Lots of room for phase error there.  Yeah I agree, check for simple wiring error. I once made a simple oscillator, didn't worked. After much time and chagrin found a one pin for pin wiring error.  All those toroids and binocs are screaming for a wrong hookup or even a short somewhere.

[W4AMV]

Hi Peter.

I am working on a somewhat similar arrangement. Using IRFP440 FETS parallel and then push pull. The FET models I have found are not always very complete especially for RF applications. Also, the coupling factor you use at K=1 just is not going to happen ! I recently built transformers for my unit and the measured K factor is 0.93. You might start there and re run your simulation. The leakage L values although small can cause issues. If you can load the actual LTSPICE schematic file that would be helpful.

73' Alan

[W3RSW]

Also have you checked real component L & C values, etc. to see if input net, say, is passing signal?

Whoops, a boarder bee is buzzing me..
Beautiful day on the deck.

[AB2EZ]

I suggest the following;

1. Check the drain bias current (the resting current with no RF input) on each FET. You can do this by placing a small value resistor in series with the bottom of L6, another in series with the top of L7, etc., and using a multimeter to measure the voltage across each resistor. Depending on how well matched the FETs are, you may have to adjust the gate bias voltages individually to obtain the target drain bias current in each FET. Note that each FET has a large transconductance. If the gate-to-source bias voltage is too low, the FET will be off. If the gate-to-source bias voltage is just a little above the turn on threshold, the FET will be fried. The setting of the gate-to-source bias voltage would be less critical if you had a small value resistor between each source and ground to provide some negative feedback. A typical value would be 0.5 ohms.

2. Since the impedance levels are relatively low, and with the RF input applied, you should be able to measure the RF portion of the gate-to-source voltage on each FET with an oscilloscope. See if each of these has an amplitude that corresponds to what you expect from the simulation.

Stu

[n1ps]

Also, the coupling factor you use at K=1 just is not going to happen ! I recently built transformers for my unit and the measured K factor is 0.93. You might start there and re run your simulation. The leakage L values although small can cause issues. If you can load the actual LTSPICE schematic file that would be helpful.

Hi Alan...true enough on the K factor.  I ran it with the unity factor as it was just easier and Ltspice seems to struggle with running anything less than that, even though it is closer to reality.  Agree on the L values and also the C leakage all adds up.  This is what I fear is the main culprit in Floyd's input design.  Note:  I cannot attach this kind of file on this forum, but I can send you a PM with it. Also please tell me more of your use of the IRFP440. I tried the 440s as I had them on hand and wanted high current devices....knowing they were nothing like a real RF FET.   Oh and another thing...I am at best dangerous with spice.   Still learning.  Amazing tool.

 

Also have you checked real component L & C values, etc. to see if input net, say, is passing signal?

Yes, all caps and inductors have been measured.

I suggest the following;

1. Check the drain bias current (the resting current with no RF input) on each FET. You can do this by placing a small value resistor in series with the bottom of L6, another in series with the top of L7, etc., and using a multimeter to measure the voltage across each resistor. Depending on how well matched the FETs are, you may have to adjust the gate bias voltages individually to obtain the target drain bias current in each FET. Note that each FET has a large transconductance. If the gate-to-source bias voltage is too low, the FET will be off. If the gate-to-source bias voltage is just a little above the turn on threshold, the FET will be fried. The setting of the gate-to-source bias voltage would be less critical if you had a small value resistor between each source and ground to provide some negative feedback. A typical value would be 0.5 ohms.

2. Since the impedance levels are relatively low, and with the RF input applied, you should be able to measure the RF portion of the gate-to-source voltage on each FET with an oscilloscope. See if each of these has an amplitude that corresponds to what you expect from the simulation.

Hi Stu....all great advice.

On 1 - I originally started with a source R (I think .1ohms), but the resistors are wire wounds and caused all kinds of fun.  This was in the original classic input using binocular feeds...which as I mentioned did work.  I also agree on the source feedback as the best way to go.  I plan to find and order some thick film TO220 types to try.  In the meantime I tried a simpler RC feedback for each FET.  Not really tested yet except in spice.  On setting the bias, I don't see any merit in measuring idle current when there really is no spec to set it to?  As this is a voltage device and we know what the threshold voltage is...that is all I can really work with....I think

On 2 - Yes gate drive looked good on the Oscope.

And to all...TNX for the comments.  I may dump this approach and go back to the more conventional binocular input feed with a balun to split the drive to the two P-P circuits.  I did not like the noise pickup around the gates on that approach and thus was intrigued by the WVL current drive approach.  To some degree the other main culprit is the 4000pf input C (!!!!).  But you will notice a tuned input which I did not use in the original version.  I had to learn how to measure input Z using spice and that was a trick to learn.

Oh and BTW, you will notice that I did not include a series gate resistor.  Whenever I inserted it using spice, it caused all kinds of issues like excessive crossover distortion.  I really have my doubts whether it is at all effective to reduce parasitics as I read about in many previous posts.

And finally...keep in mind I am just an idiot having some fun

Peter
n1ps

[W4AMV]

Hi Peter. Let me start by saying, keep it simple. Take a device like the IRF510 which has a proven track record in homebrew amplifiers. Spice simulate a very straight forward power amplifier circuit. Example, a simple L network for the input match to the FET and perhaps a PI match on the output. A single ended NMOS FET amplifier. I would then attempt to build such a unit and compare the measured response with the simulation from Spice. Point, you can do the same with the IRFP260. I did this with the 510 and the 440 and there are some disconnects. Main issue, none of the Spice level 3 models I found, have voltage dependent capacitance in their model. So, currently I am adapting these Spice models and building my own model in another simulator and patching the model based on bench measurements. This is a work in progress. Anyway try a simple class A power amplifier with your FET. Use the model in Spice and think about how you may obtain the Zin and Zout of the FET so you can design a simple matching network. When I have some time, I'll run you FET in Spice and see if I can get a Zin and Zout. Note, if I recall the Cin on this FET is ~ 5000 pF or so. 

[AB2EZ]

Peter

In the grand scheme of things, we are all idiots trying to have some fun... one way or another.

Even though there is no resting drain current level specified, for this application (a linear amplifier) it may be helpful to adjust the individual gate bias voltages so that each FET has a resting drain current of around 10% of the target drain current at carrier.

Remember, each device will follow a slightly different curve of drain current v. G-S voltage. The specification sheet says that the threshold (for 250 microamperes of drain current) is between 2 volts and 4 volts; although the range is probably tighter for devices from the same manufacturing lot.  

In my "HF Packer" linear amplifier, which uses a pair of FETs in push pull, the drain resting currents are adjusted as follows:

A) Start with both gate voltages set to zero.
B) Measure the current being drawn from the drain voltage supply
C) Adjust the gate voltage on one FET until the current being drawn increases by the desired amount
D) Adjust the gate voltage on the other FET until the current being drawn increases by the desired amount

You could do something similar to make all four(4) FETs draw equal resting currents.


Looking at the curves in the specification sheet, the gate-to-source voltage needed to obtain around 250mA (not micro amperes) of resting current with these devices appears to be around 4V... but, again, could vary significantly from device to device... and also depends on the temperature of each device inside its package, during operation.

Stu

[W4AMV]

Peter here are some notes on the IRF510 and the 440 FET. Stu's comments on the bias are spot on.  These devices usually do not Idq match unless you go to the curve tracer or check them one by one at a fixed Vgsq. I have independent VGS bias adjusts for each FET. The attached pdf takes the Spice models of the IRF510 and the IRFP440 and converts them to a data set that can be run in a commercial RF simulator. Both FETs are not stable at HF without some form of feedback. Once I determined this in the RF simulator I returned to LT Spice and verified the small signal response. This is a simple circuit and hopefully sheds some light on any disconnect between simulator, model and bench results. Bench results next...

[n1ps]

Stu - good on explanation of idle currents.  TNX.  What is the affect of an imbalance amongst a fet pair outside of one fet dissipating more heat?  Of course heat is a major concern which is why I have 2 fans.

Alan -well, you have done a lot here and I do appreciate this. Some quick comments:

Feedback - yes I have been a believer in FB with these fets all along as they are on the edge of stability.  In fact Mark, QFX and I have had numerous discussions on the subject.  He likes to use (and suggests) a form of magnetic or current feedback, similar to that shown by Granberg in several of his amps.   A question:  which method would provide the most stability?

I'm not crazy abt a series gate resistor.  Whenever I put them in the model, the waveforms become a mess.

Did you mean to include a circuit for the 440 in your PDF?  Good stuff on your Z measurements and affects of FB.

Well you got me thinking (LOL) in regard to the coupling factor and I changed to .95 on the input xformers.  What I noticed then is the xformers went into saturation (in spice)...or at least that is what I attribute the distortion to (correct?).  Increasing primary turns and reducing drive helps.  BUT...keep in mind with this type of series transformer drive, the capacity of this circuit will go up and there we go again into some unknowns. 

Getting the spice model and reality to agree or at least come somewhat close...well that is the whole point of spice I guess.  Saves a lot of soldering   Your comments on the 440 model not quite aligning with the 510 are interesting.  I have read some accounts of others who write these power fets will not work in a linear RF application.  They may be correct.  But worth the try to find out.

Ultimately I may abandon this current drive approach and go back to the more common drive.  I'll try some of the latest changes in the spice model and see how it goes.  Then down to the bench to test the smoke detectors

TNX

p

[W4AMV]

Hi Peter.
I did run simulation with both FETs and the AC response is similar. Of course the match network values quite different. All of this is pretty fundamental as this is small signal and just addressing the stability and simple match. I would do a transient analysis in LTspice to look at waveform shape and compare this to the RF simulator all with voltage drive. Good point on the waveform distortion and I need to investigate. All of this is so dependent on the quality of the NMOS FET model ! Both the 550 and the 440 models had the right set of Spice level 3 model parameters along with the data sheet that I could input a reasonable starting model in the RF simulator. This is where I found the stability factor and the input and output impedance change w/wo feedback. This really needs to be checked on the bench. If these simple items are off base in a class A application, then these models really need refined. 

[AB2EZ]

Stu - good on explanation of idle currents.  TNX.  What is the affect of an imbalance amongst a fet pair outside of one fet dissipating more heat?  Of course heat is a major concern which is why I have 2 fans.

Peter

Without providing details of how the following unfavorable effects come about (which would take up too much space here)... here are some of the unfavorable effects of not adjusting the individual G-S bias voltages on the FETs to equalize the individual drain resting currents. I am assuming that the principal mismatch between the individual FET curves of drain current v. G-S voltage is a simple horizontal offset of each actual curve (left or right) v. the nominal curve... that corresponds to the differences in their G-S threshold voltages.

1. For any given about of total peak RF output power, the linearity of the amplifier will be worse if the individual resting drain currents are not set to be equal. This will result in more IMD; and can also produce some noticeable artifacts in the demodulated output, if one push-pull FET pair turns on at a significantly different threshold voltage than the other pair.

2. In each push-pull pair of FETs, the amount of even harmonic RF power generated will be higher if the two FET drain resting currents are not set to be equal. This may result in too much 2nd harmonic RF output power getting past the output filter.

3. In each push-pull pair of FETs, unequal drain resting currents will produce significantly increased core saturation in the transformer that combines the push-pull outputs... resulting in increased non-linearity, excessive core heating, and increasing the tendency toward instability.

You should be able to simulate these effects by using identical FETs in your LTspiceIV simulation, but using different G-S bias voltages on the various FETs. For example: try using a G-S bias voltage that results in 50mA of resting drain current in the top FET of the 1st push-pull pair, and 500mA of resting drain current in the bottom FET in the first push-pull pair. In the other push-pull pair, use a G-S bias voltage that results in about 250mA of resting drain current in each of the two FETs.

  Stu

[W4AMV]

Peter,

I am collecting some design notes and simulations for the 510 and 440 FETs. I was wondering what is you operating frequnecy? Single band or the entire HF band ? Both FETs present a challenge much above 14 MHz. On your question for the transformer feedback, I was going to address that item in this note. Also your comment on the series gate resistor, this should be addressed. A reference to this application is EB104 from Motorola, see FIG 2. Note the independent bias for the FETs. I'll see if I can find a link.

Alan
Here is one link to the note, there are others.
http://www.ab4oj.com/dl/eb104.pdf

[n1ps]

Very good Alan.  Initial app is for 3.85 MHz.  Note the input has a band pass filter.   At most I will add a second band for 7.  I have not had any time to get back on this...but may do some more Saturday.  Yes familiar with EB104.  I don't know how critical the individual bias is as I have seen all sorts of designs.  For example, would mismatched FETs cause some distortion or cause the amp to not work at all?  I tend to think it is the former, but not certain at all.

A question...can these modeling programs indicate parasitic oscillations?  I tend to think no because layout plays a role (that would be a big role) there.  But curious.

I also wonder whether the modelling program is effective as this FET (and similar) was not designed for this service at all.  But I like your idea of modelling a known RF transistor and doing a comparison.

p

[Opcom]

I'm always glad to see this experimentation and research go on. If it causes horror among some application engineers, it's because they don't see what's really happening and why. So keep it up!

[W4AMV]

Thanks Peter for the information.

I'm always glad to see this experimentation and research go on. If it causes horror among some application engineers, it's because they don't see what's really happening and why. So keep it up!

And of course this is Fun. I ran a number of simulations and the results are reasonable and informative. It will take me some time to collect and add comments. Worthy of note is the work done by all the Class E folks as well and nice job of documentation that W6JL Donald Huff did as part of the QST homebrew contest, 2010. The FETs used there are IRFZ24N as well as the IRFZ34N. He used an IRF model in LTSpice and documented to some degree model vs. simulation. The commercial simulator I am using adds quite of bit of insight and that motivates me to document the results. You asked about parasitic oscillations. LT Spice handles oscillators very well. So if you can model the parasitic well, then sure. You might try an experiment with a simple amplifier, say using a bipolar device within LTSpice library and add a parasitic. Check out the transient response and see if the oscillation is present. The tricky part is setting up the transient conditions for the analysis.

One final comment for now. Although the results with shunt feedback applied to the IRFP440 are resonable, the tradeoff of gain for stability may be more than I desire. Either the xmfr feedback mentioned would be better or as Don used, the heavy shunt loading on the gates. I plan on comparing and then finally build something.

Alan

[W4AMV]

Peter,
Here is a set of notes on the push pull amplifer that I have pulled together. There are simulations that I have not seen that should be of interest. There is a short discussion on transformers, power and efficiency. Hopefully it will answer some of your questions and probably raise new ones. The transformer feedback and the parallel FET push pull arrangement is to be added and build to compare is required.

73' Alan

[n1ps]

TNX Alan...I have not had a chance to get back into the project...busy at work, golf season started and yard work.  But hope to do some testing this weekend at some point.  I'll also read your doc in detail.  Looks very interesting!

Peter

[W4AMV]

Very good Peter.

Find attached the schematic for the parallel PP IRF510 FETs. You can duplicate this schematic in LT and use their 510 MOS model. Interesting that this simulation WILL SHOW a parametric oscillation, the odd mode instability which can occur in PP amplifiers. Remove the 100 ohm drain to drain strapping resistor and re run the simulation to see the issue. This simulation will provide 100 W out and was run on the 40 M band. The xmfr values are near the 4:1 and 2:1 ratio mentioned earlier and the initial work was done in the other simulator. There should be a 50 ohm load at Vout terminal. At 5 W in the Pout is ~ 95 W

Alan