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Author Topic: Oscillations associated with capacitors in parallel  (Read 3543 times)
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AB2EZ
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« on: June 04, 2011, 11:15:25 AM »

I was doing some "tweaking" on my 1-FET Class E transmitter. I noticed that the Drain-to-Source voltage waveform looked like a Class E waveform is supposed to look... and everything behaved properly as I adjusted the loading capacitor in the tank circuit of the transmitter. However, I did see a relatively high frequency (~ 50MHz), low amplitude parasitic sine wave superimposed upon the Drain-to-Source waveform. It was superimposed on the entire waveform (both the positive part of the voltage waveform that exists during a portion of each half cycle of the fundamental frequency of operation when the FET is "off", and the flat part of the waveform that exists for the remainder of each cycle of the fundamental frequency of operation).

I attached a photo of the oscilloscope display after I initially made this post. The blue trace is a sample of the Drain-to-Source voltage. The yellow trace is a sample of the output of the transmitter (at carrier level, with no modulation applied). In both cases, the scaling is 1000:1 (50 mV on the display corresponds to 50 Volts between the actual circuit nodes)

After convincing myself that this was not an artifact of the measurement setup I was using, I had a chance to think about what this superimposed, parasitic sine wave was. Some quick calculations verified that this superimposed parasitic sine wave would dissipate several percentage points of the total input power... and thus reduce the efficiency of the transmitter by several percent (or more).

What I think is happening is something that would happen whenever two (or more) capacitors are placed in parallel ... whether in the case of a Class E transmitter, or a traditional transmitter with (for example) a tuning capacitor in parallel with a padding capacitor.

Refer to the attached drawing

The 260 pF capacitor represents the typical Drain-to-Source capacitance of an 11N90 FET. The 150pF capacitor is a doorknob capacitor added to bring the total parallel capacitance up to 410pF... which is what the formulas for Class E transmitter design suggest is optimal for the average Drain-to-Source voltage, average drain current, operating frequency etc. that I am using.

The "pulse current source" represents the pulses of current that are injected into the capacitors via the switching process (i.e. applying an r.f. signal between the gate and the source to turn the FET on and off at the fundamental frequency of operation).

The loop consisting of the two capacitors and the interconnections between the two capacitors (top and bottom) represents a high Q resonant circuit whose resonant frequency is determined by the values of the capacitors... and the total inductance of the connections between them. The length of the top and bottom connections added up to around 3".

With a little reverse engineering... I concluded the the required inductance to result in a resonance at 50MHz was somewhat less that 0.05 microHenries.

By shortening the length of the connections to around 1.5" (total), I was able to significantly reduce the amplitude of this parasitic sine wave... and the efficiency of the transmitter increased by several percent.

It probably would be even better to incorporate some sort of parasitic suppression method. For example, by making the top connection (which is a wire in this case) a smaller gauge wire, one could increase the skin effect at higher frequencies... and possibly damp out (to some extent) the high frequency oscillation. However, this would also increase the resistive loss of this connection at the desired frequencies... so the net effect would be to make the efficiency worse.

Stu


* Oscillation.jpg (31.3 KB, 960x720 - viewed 425 times.)

* 1 FET Class E 001 Compressed.jpg (50.19 KB, 448x336 - viewed 446 times.)
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Stewart ("Stu") Personick. Pictured: (from The New Yorker) "Season's Greetings" looks OK to me. Let's run it by the legal department
steve_qix
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« Reply #1 on: June 04, 2011, 12:11:20 PM »

Hi Stu,

Interesting !!!!  Any chance of you posting the actual waveform you're looking at?
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Patrick J. / KD5OEI
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« Reply #2 on: June 04, 2011, 12:19:53 PM »

That is a very good analysis. You have an extra little tank circuit going. How about putting a very small ferrite bead over the normal wire to lower the Q of the parasitic circuit and dissipate some of the oscillation? Or would that be worse for the operating frequency? You mentioned 50KHz  and then 50MHz so I am more confused than usual. The next question might be the type of doorknob capacitor in use and its internal inductance. Would the kind used in VHF amplifiers help? (the flat square ones with tabs)
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AB2EZ
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« Reply #3 on: June 04, 2011, 12:49:23 PM »

Steve

I am charging up the battery on my camera. I will add a picture of the actual oscilloscope waveform (associated with the shortened connecting leads... but still showing a reduced level of the effect) to my original post... a little later today

Patrick

Thanks for pointing out my error (50kHz => 50MHz). I corrected my original post. I'm using a doorknob capacitor that I purchased from a fellow in the Ukraine:

http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=400208024169&ssPageName=STRK:MEWNX:IT

The capacitor may have some inductance... but when I cut the length of the connecting wires approximately in half... the frequency of the superimposed parasitic sine wave went up by a factor of 2 (from 14 cycles per period of the fundamental frequency to 28 cycles per period of the fundamental frequency)... and its amplitude went down. Also, having shortened the connecting wires, the parasitic sine wave now seems to be attenuating noticibly during the flat part of the fundamental frequency cycle of the Drain-to-Source voltage waveform. I'm going to try shortening the interconnecting leads even more. Based on this, I think the interconnecting leads are/were the problem.

Stu
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« Reply #4 on: June 05, 2011, 09:56:15 PM »

Stu,
I have seen this a number of times and exactly the reason I am so anal about circuit layout. Inductive orange drop caps are an example of trouble waiting to happen in an RF circuit.
Also I have seen active dielectric materials like XR7 actually drop to 1/2 "C' value when pulsed with high current. It can also ring. 
I've seen 250 kHz switchers generate harmonics to over 100 MHz when the layout was not right.
It is a whole new world when you get a scope that will display 1GHz.
I was having some problems with a custom EMI filter we use at work. Simulation showed an extra 25 nh of inductance in the case ground termination costs 25 dB of attenuation above 50 MHz.
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