The SiC fets work well when all is well, so to speak. They don't have the SOA characteristics of a standard MOSFET, and therefore are much more intolerant of any sort of current overload. So do be wary of that when designing.
I've been able to achieve VERY high efficiency due to the low R D-S on in experimental implementations.
The drive is more critical for sure. The devices don't saturate like a silicon MOSFET, so absolutely as much drive as is possible will be critical. Without that, you will notice nonlinearity under modulation, and also random failures on peaks due to die heating.
Just my experience..
I need to watch out for sounding more like an expert than I am... I have an electronics background, but specc'ing FETs for conventional circuits is one thing, exotic stuff like this is another. So, I'm still learning what makes a good Class E FET, and definitely listening to the experienced folks like you and Nigel.
I compared the two SOA graphs, they are rather different. Kind of strange they don't show a DC line on the Cree FET?
So far, Ive only done "couch testing", running LTspice simulations... no real world yet. I am using the Cree model for the FET we're talking about, (which is supposed to be very good) and think I see the unsaturated effect. Gate voltage matters. Oddly, even after much tuning around I only get efficency in the low 80's, with a single FET. I easily see mid 90's using other Si FET models. Of course, simulation is only as good as your model, and more, being a good match to reality....
A question, do any of you do any drain current waveform measuring? I've had a little bit of workplace experience in Class E like stuff on a wireless charging system, and I found looking at both the current and voltage waveform more insightful when tuning. Been researching DIY ways to do this cheaply and noninvasively...