Optimal load resistance for FETs

[ka1tdq]

For designing a 250 watt carrier, Class C RF deck with 4 FETs in parallel:

Vdd=48 volts

250 watts/48 volts = 5.2 amps

5.2 ohms/.7 (efficiency for Class C) = 7.5 amps

If the optimal load resistance for a FET is (.5 x Vdd)/Icarrier then:

(.5 x 48 volts) / 7.5 amps = 3.2 ohms

If I use a 1:2 (one turn to two turn transformer on a 43 material core) then I get a 1:4 impedance transformation.

My 3.2 ohms becomes 12.8 ohms.  

I'm looking for a 50 ohm match, but since I'm using 4 FETs in parallel my ideal load resistance is 50 ohms/4 or 12.5 ohms.

So, 12.8 ohms out of the transformer is very close to 12.5 ohms.  

Will this work?

Jon
KA1TDQ

[AB2EZ]

Jon

This is not correct:

"I'm looking for a 50 ohm match, but since I'm using 4 FETs in parallel my ideal load resistance is 50 ohms/4 or 12.5 ohms.

So, 12.8 ohms out of the transformer is very close to 12.5 ohms."


If your antenna has a [50  + j0] ohm impedance, you will need a matching network that to convert [50 + j0] ohms to the optimal class C load impedance on the FETs (i.e. 3.2 ohms); and, preferably, to pass primarily the fundamental RF frequency (i.e. to significantly block the harmonics).

Alternative 1: If you don't care about blocking the harmonics, because you are confident that you will sufficiently block harmonics in the combination of your antenna tuner and your antenna, you could use a 1:4 transformer to convert 50 ohms to 3.125 ohms.

Alternative 2: Use a combination of a 1:4 transformer (as in alternative 1), and a low pass LC filter [to produce a relatively small drain voltage response to the harmonics of the drain current waveform... by presenting a low input impedance (compared to 50 ohms) at harmonic frequencies]. There are various low pass LC filter designs in the published schematics of solid state RF transmitters and RF amplifiers (homebrew and commercial), as well as filter design applications that are available for free.

http://www.calculatoredge.com/electronics/ch%20pi%20low%20pass.htm

Alternative 3: Make this a class E transmitter by using the 1:2 transformer, followed by a tuned series LC network, feeding: [a variable loading capacitor in parallel with your (approximately) 50 ohm antenna load]. You will then obtain the following results:

1. The variable loading capacitor, C(loading), when adjusted to have a capacitive reactance of around -j28.9 ohms (for example), in parallel with the 50 ohm antenna load, looks like (equivalent circuit): 12.5 ohms (resistive) in series with j21.7 ohms of inductive reactance.

2. The tuning capacitor, C(tuning) in the series tuned circuit, can series resonate: Z_l(total) = the inductive reactance of the tuning coil + j21.7 ohms). By using a (fixed inductance) tuning coil with sufficient inductance to make Z_l(total) = j125 ohms at the fundamental RF frequency, you will have a series tuned circuit with a Q of 10.

Example

Fundamental RF frequency = f = 7.3 MHz

1/[j x 2pi x f x C(loading)] = -j28.9 ohms => C(loading) = 754pF

j x2pi x f x L(tuning) +j21.7 ohms = j125 ohms => L(tuning) = 2.25uH

1/[j x 2pi x f x C(tuning)] = -j125 ohms => C(tuning) = 174pF


The 1:2 matching network will (as you stated) step down 12.5 ohms to 3.125 ohms

By adjusting the loading capacitor and then adjusting the tuning capacitor, you can produce the correct RF load on the FETs for class E operation.

Note: In the case of a class E transmitter, you are depending upon the total drain-to-source capacitance of the FETs to limit the FET load impedance at harmonics of the fundamental frequency. You may have to add some fixed capacitance, from drain-to-source, to keep the peak (each RF cycle) voltage from drain-to-source from getting too large.

Stu

For designing a 250 watt carrier, Class C RF deck with 4 FETs in parallel:

Vdd=48 volts

250 watts/48 volts = 5.2 amps

5.2 ohms/.7 (efficiency for Class C) = 7.5 amps

If the optimal load resistance for a FET is (.5 x Vdd)/Icarrier then:

(.5 x 48 volts) / 7.5 amps = 3.2 ohms

If I use a 1:2 (one turn to two turn transformer on a 43 material core) then I get a 1:4 impedance transformation.

My 3.2 ohms becomes 12.8 ohms.  

I'm looking for a 50 ohm match, but since I'm using 4 FETs in parallel my ideal load resistance is 50 ohms/4 or 12.5 ohms.

So, 12.8 ohms out of the transformer is very close to 12.5 ohms.  

Will this work?

Jon
KA1TDQ

[ka1tdq]

Ok, great info! This gives me lots to think about for my final design.

But, I guess that paralleling FETs doesn't have any impact on output impedance? For example, say a single tube is 2500 ohms. Paralleling a second tube brings that down to 1250 ohms to match.

And, I'm thinking that I would just need a .5 watt RF drive source at 50 ohms to drive a digital drive IC (DD614). This would give a 5 volt peak signal.

5 volts/50 ohms = .1 amps

.1 amps x 5 volts = .5 watts

Jon
KA1TDQ

[AB2EZ]

Jon

Your calculation of the optimal RF load impedance for the FET's in class C operation (3.2 ohms) was correct. With the same drain-to-source voltage, and 4x the average drain-to-source current (vs. that of a single device), you get 1/4 the result for the optimal RF load impedance that you would obtain for a single FET. This is just as in the case of tubes operating in class C. Each individual device "sees" the same drain-to-source voltage, but only 1/4 of the total drain current... therefore each individual device "thinks" it is looking into 4x the RF load impedance (12.8 ohms) at the fundamental frequency.

What was wrong in your first post was the assumption that somehow your actual system antenna input impedance (50 + j0 ohms) should be divided by 4 before calculating the required matching network. The input impedance of the antenna system is 50 + j0 ohms, at the fundamental frequency, regardless of what source is driving it.

Since the antenna system doesn't know what is driving it, and the FETs don't know what they are driving into... all that matters is that the 50 + j0 ohm antenna system input impedance must be transformed into a 3.2 + j0 ohm impedance (at the fundamental RF frequency) by the matching network (including the transformer). Since the total drain current is split 4 ways, each individual FET will be "looking into" 4 x (3.2 + j0) ohms = 12.8 + j0 ohms. [i.e. Z= V/I]

Stu

Of note:

The objective, in the case of class C operation, is to maximize the voltage swing... at the fundamental RF frequency... that is produced by the time varying drain current waveform. The time varying drain current waveform is proportional to the time varying drain-to-source voltage, provided the drain-to-source voltage doesn't drop to zero volts (or reverse polarity v. normal operation). Therefore, we want to pick the RF load impedance, at the fundamental RF frequency, such that: (the amplitude of the fundamental frequency component of the total time varying drain current waveform) x (the RF load impedance at the fundamental frequency) = the DC drain voltage. In addition, we want the drain-to-source load impedance at harmonics of the fundamental frequency to be much lower than the RF load impedance at the fundamental frequency. This will ensure that the time varying portion of the drain current does not produce any significant changes in the drain-to-source voltage, except at the fundamental RF frequency.

From Fourier analysis: in the case of class C operation... the amplitude of the fundamental frequency component of the total time varying drain current waveform (or the total time varying plate current waveform, in the case of a tube) is approximately 2 x the average drain current

Therefore, we obtain the equation that you used:

a. The optimal RF load impedance at the fundamental RF frequency = Vdc/(2 x Idc) = 0.5 Vdc/Idc

b. The load impedance at harmonics of the fundamental RF frequency should be much less than 0.5Vdc/Idc

The analysis for class E operation is different, for several reasons, even though it produces a similar result for the optimal RF load impedance, at the fundamental frequency, as is produced in the class C analysis. For example, in class E operation (unlike class C operation), the time varying portion of the drain-to-source voltage waveform is not a sine wave at the fundamental RF frequency... because the drain-to-source RF load impedance is not close to zero at harmonics of the fundamental RF frequency.

Ok, great info! This gives me lots to think about for my final design.

But, I guess that paralleling FETs doesn't have any impact on output impedance? For example, say a single tube is 2500 ohms. Paralleling a second tube brings that down to 1250 ohms to match.

And, I'm thinking that I would just need a .5 watt RF drive source at 50 ohms to drive a digital drive IC (DD614). This would give a 5 volt peak signal.

5 volts/50 ohms = .1 amps

.1 amps x 5 volts = .5 watts

Jon
KA1TDQ

[WQ9E]

But, I guess that paralleling FETs doesn't have any impact on output impedance? For example, say a single tube is 2500 ohms. Paralleling a second tube brings that down to 1250 ohms to match.

Jon
KA1TDQ

Jon,

Your example of paralleling a second tube to bring down the impedance to roughly half is only true if you are doubling the power via the added capability of the second tube.  If the circuit in question is running at 500 watts input and you add a second tube while maintaining the same power level then you aren't materially changing the plate load.

[ka1tdq]

In the Navy, those were called "GCE's" (Gross Conceptual Errors). After thinking about it, output impedance wouldn't change simply by adding the second device at the same power level. Current through each device would decrease though.

I know this is a sin, but I was considering building a 40 meter CW transmitter at 250 watts. I could practically use a Tuna Tin II to drive the DD614.

Jon
KA1TDQ

[ka1tdq]

...or back to the idea of a 4-FET class C 40 meter RF deck, analog driven by a rice box:

To Heising modulate such a beast, and going by formulas from a previous thread:

Rmodulation = 48 volts / 7.5 amps = 6.4 ohms

Choke:  .25H x (Rmodulation / 50 ohms) = .25H (6.4/50) = .032H

Capacitor:  100uF x 50 ohms / Rmodulation = 100uF x 50 / 6.4 = 782uF

Does there exist a .032H choke that can handle 7.5 amps?

If I could source that along with a honkin'-huge audio amp, I'd be in business.

Jon
KA1TDQ

[ka1tdq]

http://www.ebay.com/itm/Choke-choke-transformer-05-Hy-5-ohms-High-amps-/151225341033?pt=LH_DefaultDomain_0&hash=item2335bb9469

Would this do it?

[WBear2GCR]

Stu,

You said:

In the case of a class E transmitter, you are depending upon the total drain-to-source capacitance of the FETs to limit the FET load impedance at harmonics of the fundamental frequency.

Not sure what you mean by "...the FET load impedance..."?
Limiting going higher, lower?
Only WRT how the FET is seeing a load at harmonic (higher) frequencies??

This is probably straightforward enough but at least I am uncertain what is being referred to?

Tnx.

              _-_-

[AB2EZ]

Bear

In a class C RF amplifier, driven by a periodic gate-to-source (ground) input voltage, there is a path to ground for those (Fourier series) components of the time-varying (periodic) drain current* that are at multiples of the fundamental frequency (i.e. components of the drain current* at harmonics of the fundamental frequency). This path to ground, for currents at multiples of the fundamental frequency, is provided by the capacitor between the drain and the source (ground) at the input of the low pass filter; and this path to ground has an impedance that is (as an objective) much lower than the impedance looking into the low pass filter at the fundamental frequency. Therefore, the non-sinusoidal periodic sequence of pulses of drain current* produces a DC + sinusoidal (at the fundamental frequency) voltage between the drain and source (ground).

In a class E RF amplifier, the series tuned circuit between the drain and the loading capacitor/RF output connector produces a high impedance path for components of the drain current* that are at multiples of the fundamental RF frequency. These components of the drain current* will flow through the combination of the internal drain-to-source capacitance of each FET plus any external capacitance between the drain and ground that has been added. The impedance of this capacitive path from drain-to-source (ground) is intentionally made high enough, at the harmonics of the fundamental RF frequency, to produce the nominal class E periodic drain-to-source voltage waveform (which is not a DC + a sinusoid).

However, if this total capacitance is too low, the peak drain-to-source voltage of each of the periodic class E pulses may be too high. Therefore, one has to ensure that there is enough added capacitance between the drain and the source.

*In the above, "drain current" refers to: the DC flowing into the drain node from the power supply - the total current flowing from drain-to-source within the FETs. Therefore, it is the current that must flow from the drain node to the source node (ground) via whatever external load is connected between the drain and the source.

Stu

[ka1tdq]

I've attached an initial sketch of the RF deck.  I didn't include the Transorbs for clarity, but imagine that everything is protected.  Borrowing from the Class E website, I put 4 ferrite cores on the output to handle the power. 

I have large 12 volt transformers that I got from Goodwill for next to nothing.  I can run them in phase and in series to get to 48 volts.  The good thing is that during testing, I can tap 12 volts at a time to make sure nothing blows up.

Jon
KA1TDQ

[WBear2GCR]

Jon,

Thought I'd mention that if you set up the 4 devices as two pairs, running in Push-Pull, rather than parallel you would get some automatic cancellation of the even order harmonics.

Stu, I will read that again later when my brain is in the higher absorption state.

                         _-_-

[W3RSW]

Shouldn't the fet sources have some load balancing resistance, say 0.1 ohm or so?

[ka1tdq]

I re-drew the schematic to be push-pull pairs.  Say that without spitting.

How does this one look?

[AB2EZ]

Jon

The turns ratio for each of the output transformers is not correct in your draft push-pull design.

Since the power is the same, the peak of the sinusoidal voltage (at the fundamental frequency) waveform, V_peak at the input to the filter is the same as in the 4-FET single ended design. I.e. total power = 0.5 x V_peak x V_peak / 50 ohms

This means that the peak voltage (at the fundamental frequency) across each of the transformer secondary windings is: V/2

Each FET is drawing the same average current as before, and producing the same RF output power as before... so the peak of the sinusoidal voltage (at the fundamental frequency) waveform across the primary winding of each of the output transformers has to be the same as in the 4-FET single-ended design.

This means that the voltage step up ratio of each transformer in the push-pull design has to be half of what it is in the single ended design.

Therefore the turns ratio for each output transformer should be 1:2 in the push-pull design (v. 1:4 in the single ended design)

Also, I agree with Rich that a balancing resistor is needed, between source and ground, of each FET. Each balancing resistor has to be non-inductive (able to pass at least 4x the fundamental frequency with very low inductive reactance), and should have a value of around 0.1 ohms [as per Rich's (W3RSW's) suggestion].

Note that: 0.1 ohms x [approximately (7.5 amps/4) of DC per FET] x (approximately 4 amps of peak current per amp of average current) = 0.75V of peak negative, gate-to-source feedback voltage... when the currents are balanced. Using 0.2 or 0.25 ohm balancing resistors might be even better... although this increases the required gate drive voltage.

Stu  

[ka1tdq]

I figured the output turns ratio would change in a push-pull configuration compared to the single ended design, but I wasn't quite exactly sure.  Thanks for the info.  I'll do 2 turns secondary and put in source lead resistors. 

I'm going to the Tucson hamfest this weekend and will start looking for parts for this project.  I was originally thinking about using Heising modulation for this project too, but I was reading about some problems doing that.  Another person used a 'modulation' transformer for a high powered Class D transmitter and he had a large power spike on the modulator input during key-up.  He said this could destroy his audio amp.  And audio amps at that power level aren't cheap.

I'll worry about modulation later.  First I'll get the RF stage built and working. 

Jon
KA1TDQ

[AB2EZ]

Bear
et al.

Attached is a conceptual drawing of a class C FET RF amplifier

For simplicity, the drain current is shown as a periodic sequence of square pulses, each 1/8 cycle in duration, having an average value of 1 ampere.

The current i₁(t) is the current that flows into the "load" between the drain and the source... including the drain-to-source capacitance of the FET.

This conceptual drawing may be helpful in digesting my earlier posts in this thread.

Note that the sinusoidal component (not explicitly shown) of the waveform i₁(t), at the fundamental frequency, has an amplitude of approximately 2x the average value of the drain current. I.e. the amplitude of the fundamental frequency component of i₁(t), in this example, is 2 amperes.

Stu

[WBear2GCR]

Jon,

I'm thinking that the output transformer doesn't look quite right to me.
Kinda think that part of the idea is that the two halves share the core.

There is a similar design that was a QST article and is on the web somewhere, it's being sold as a kit, or was, called the EB-104, iirc. Used two MRF150 in the output.

Might be a starting point for comparing how others have done it with what you want to do?

               _-_-bear

www.ab4oj.com/dl/eb104.pdf

more... nice build too! ---> http://www.g4apvweb.pwp.blueyonder.co.uk/

[ka1tdq]

That kit is available for $320 for everything (less power supply).  It comes with the pre-wound transformers too.

I guess it would be possible to leave off the gate biasing components (R11, R12, R13, R14 and everything back of them) and just use a carrier to drive the board Class C.  Then, just modulate the Vds.

Jon
KA1TDQ

[WBear2GCR]

I don't think that a simple modulation of Vds will work as planned.

One issue will be not exceeding the Vds rating of the devices.
The other issue will be how the devices function (do they stay linear) when the
voltage applied goes "low".

Seems like one might need to drop the supply voltage considerably if one wanted to modulate the actual final via the supply voltage itself.

But assuming one could overcome those points, then it might fly - but I am no expert in this area.

                           _-_-

[ka1tdq]

You're right, and I didn't think about that. You can't exceed 50 volts on some of those devices.

I'm still trying to get a good idea for my next project, but nothing has jumped out at me yet.

Jon
KA1TDQ