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Class E drive and Duty Cycle for drive




 
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Author Topic: Class E drive and Duty Cycle for drive  (Read 1765 times)
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M0VRF
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« on: November 25, 2020, 06:17:49 AM »

I'm sure Ive read somewhere 40% was the optimum drive level for diving the gates for class E.

I'd like confirmation as cant find the relative text on here or Steves website.

Could anyone point me towards and relative info?

Would be much appreciated.

Regards

J.
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vk3alk
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« Reply #1 on: November 25, 2020, 05:30:59 PM »

Hi J.

Steve mentions it in the VFO part on his WEB site......

This article here https://people.physics.anu.edu.au/~dxt103/160m/class_E_amplifier_design.pdf probably has it but I don't seem to have the patience to read it anymore....


Wayne
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steve_qix
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« Reply #2 on: November 25, 2020, 11:13:09 PM »

Yeah, 40% at the gates is good.  As the duty cycle increases, the efficiency will go down somewhat.  This pertains to standard MOSFETs.   SiC MOSFETs actually work better with a duty cycle closer to 50% at least in my experience.

I did mention it on my site, but only in passing and in the VFO project overview.  I suppose it should be more front and center.
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ka1tdq
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« Reply #3 on: November 26, 2020, 12:10:18 AM »

Don't fret too much about the exact number. I've made some really pretty waveforms with Chinese VFO's and guesswork. Class E is very forgiving to a certain extent. I started with a single FET rig and learned about everything by watching the gate and drain waveforms as I varied stuff. After that I felt confident to move onto the 8-FET version. I built a 24-FET rig after that but only put it on the air once. It scared me. Eight FETs in an enclosed chassis is good enough.

Jon

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M0VRF
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« Reply #4 on: November 26, 2020, 03:22:39 AM »

Thanks for the info.

I have 43% so will be happy with that.

Interesting that 50% is better for SiC, thanks for that Steve.

Regards to All.

J.
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