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AB2EZ
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« Reply #25 on: January 07, 2015, 05:19:06 PM »

Jon

Some additional information:

If the 5A average FET drain current were an ideal square wave, toggling between 0A and 10A, then the peak-to-peak, fundamental frequency, sinusoidal component of that square wave would be 10A x 4/pi = 12.7A (Yes, the sinusoidal component of a square wave has a peak-to-peak value that is 1.27 x the peak-to-peak value of the square wave). The corresponding  RF output power would be 40.5 watts (with a 2 ohm RF load). The electrical input power would be 13.8V x 5A = 69 watts.

If the 5A average FET drain current were an ideal rectangular wave, on 75% of the time and off 25% of the time, toggling between 0A and 5A/0.75 = 6.67A, then the peak-to-peak fundamental frequency, sinusoidal component of that rectangular wave would be 6.67A x (2/pi) x [sin (0.25 x 2pi)] = 6.67A x (2/pi) x (1) = 4.24A. The corresponding RF output power would be 4.5 watts

If the 5A average FET drain current were an ideal rectangular wave, on 80% of the time and off 20% of the time, toggling between 0A and 5A/0.8 = 6.25A, then the peak-to-peak fundamental frequency, sinusoidal component of that rectangular wave would be 6.25A x (2/pi) x [sin (0.2 x 2pi)] = 6.25A x (2/pi) x (0.95) = 3.784A. The corresponding RF output power would be 3.57 watts.


If the 5A average FET drain current were an ideal square wave + a DC, toggling between 3.5A and 6.5A, then the peak-to-peak fundamental frequency, sinusoidal component of that square wave would be 3A x (4/pi) = 3.82A. The corresponding RF output power would be 3.65 watts.


Stu
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« Reply #26 on: January 07, 2015, 05:32:56 PM »

So duty cycle makes a huge difference. I guess I should shoot for that perfect square wave.

Jon
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« Reply #27 on: January 08, 2015, 02:49:33 PM »

...just a thought

Does the IXYS need a switching rail voltage at the input?  13.8vdc on/off?  Steve's class E version shows 12 volts switching input with a 12 volt supply.

Also borrowed material, but I drew this schematic that could go in between the oscillator output and the IXYS input.

Jon


* IMG_0160.JPG (1775.01 KB, 3264x2448 - viewed 469 times.)
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« Reply #28 on: January 08, 2015, 04:23:15 PM »

The IXYS driver ic doesn't require a switching stabalisator ic, just a linear one is good enough. The driver current is 100mA to 200mA depending on the gate charge of the mosfet . You can use an linear voltage regulator like an 7812 or 7815.
If the output is low use an another output transformer 1:2 will mostly good enough.

Martin
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« Reply #29 on: January 08, 2015, 10:52:27 PM »

I re-did everything except the 7806 for the oscillator board.  I unsoldered the 7805 but looked closely at what All Electronics out of California had sent me.  The warehouse guy needs glasses or something because they sent me 7808's instead. 

I did test the new IXYS configuration with the 5 volt regulator in there (before I unsoldered it) and I'm getting 4 watts out.  A slight improvement but nothing near what I should be getting.

I'm going to get some 7806's from DigiKey, but in the meantime, could I put an FT37-43 in between the IXYS and the gate?  Maybe put 4 turns primary to 8 turns secondary to double the voltage driving the FET?

Jon
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* IMG_0162.JPG (2691.04 KB, 3264x2448 - viewed 453 times.)
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AB2EZ
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« Reply #30 on: January 09, 2015, 12:54:58 AM »

Jon


I don't see the twisted pair transmission line between the oscillator (inverter output bus + inverter ground) and the IXYS chip (input pin 4 + ground pin 3).

As before, if the IXYS chip is working properly, the measured DC voltage between its output pin and ground should be something like 0.5 x 13.8V.

I suspect that you will need an oscilloscope to go much further in troubleshooting this circuit.

Stu

 
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AB2EZ
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« Reply #31 on: January 09, 2015, 11:53:47 AM »

Jon

Additional suggestion:

The 100 ohm resistor that is intended to be a load on the output of the oscillator (inverter) is presently connected as follows: output of the oscillator (inverter chip) => pin 4 of the IXYS-chip => 2" of resistor lead length and resistor body=> a point on the shared ground plane => a long path back to the ground of the oscillator (inverter) chip, via the ground plane.

While this seems like a complete circuit that follows the schematic, the large area enclosed by this path can result in a large voltage induced around this path by the magnetic field associated with the large current that is returning to pin 3 (ground) of the IXYS chip via the ground plane. Furthermore, inductance of the portion of this closed path that is shared with the path being taken by the IXYS output ground return current can also introduce large voltages around this path. Remember, all of the IXYS chip output current is flowing into the gate of the FET, and then flowing back from the source of the FET into the IXYS chip's ground pin. This IXYS chip output current is much larger than the current flowing through the output wire (and back) of the oscillator.

I suggest that you tack a 1/4 watt, 100 ohm resistor (physically much smaller than what you have now) between pins 4 and 3 (with leads as short as possible), instead of using the physically large resistor and the wiring approach you have now. The required dissipation capability of this resistor (with a 50% duty cycle 0-to-5V square wave across it) is roughly: 0.5 x 5V x 5V/100 ohms = 0.125 watts. This, combined with the use of a twisted pair between the oscillator and the IXYS chip, will reduce the area enclosed by the round-trip path between the oscillator and the IXYS chip, and will mostly remove any portions of this closed path that are shared with the IXYS output current ground return.

From the IXYS data sheet:

GROUNDING

In order for the design to turn the load off properly, the IXDD414
must be able to drain this 5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD414
and it’s load. Path #2 is between the IXDD414 and it’s power
supply. Path #3 is between the IXDD414 and whatever logic
is driving it. All three of these paths should be as low in
resistance and inductance as possible, and thus as short as
practical. In addition, every effort should be made to keep these
three ground paths distinctly separate
. Otherwise, (for
instance), the returning ground current from the load may
develop a voltage that would have a detrimental effect on the
logic line driving the IXDD414.


OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the load.

Stu
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« Reply #32 on: January 09, 2015, 01:28:16 PM »

Ok, that's an easy changeout.  My building will need to be put off for about two months though. I just had a cast put on my soldering arm and hand this morning. It makes typing a real bear too.  But, eh, stuff happens...

Anyway, I'll post another update when I can make it happen.

Jon
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AB2EZ
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« Reply #33 on: January 09, 2015, 02:22:14 PM »

Jon

Ugh!

Heal quickly!!!

Stu
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« Reply #34 on: January 13, 2015, 08:55:05 AM »

I did do one easy change that I could do with my right hand. I clipped the Transorbs from the gate of the FET.  Power increased from 3.5 watts to 7 watts. Power also rises as I hold key-down and things warm up. I don't think I'm in danger of exceeding 18 volts on the gate, so I could probably leave this disconnected.

I'm going to change the 100 ohm resistor configuration with twisted pair lead and shorter attachments to the IXYS.  I don't want to do it with my cast on because I'll butcher it for sure. It comes off in 3 weeks, so I guess I can wait.

**One other quick question:

I have the back tab of the IXYS currently isolated from ground via a mica spacer.  From the pictures on the class E website, it looks like they're attached to ground.

---Found the answer:    "The ground terminals of each driver ICs are connected directly to the source bus, and the tab (also ground for the driver ICs) is bolted directly to the heat sink." (per the class E site)

Jon
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AB2EZ
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« Reply #35 on: January 13, 2015, 12:31:59 PM »

Jon

I thought there was something funny in the schematic regarding the gate TransZorb(R) devices.

From the photo (no stripe on either side), and from the part number in the schematic (1.5KE18CA), I believe that the devices you are using are bidirectional type.

The schematic makes them appear to be unidirectional types. In the schematic, one of them (if it were unidirectional) is forward-biased... providing a conducting path from gate-to-source.

In any event, you should only have one bidirectional device from gate-to-source (not gate-to-a distant ground). The second, parallel device (shown in the schematic as a forward biased Zener diode, which would be the wrong direction if it were a unidirectional type) is not necessary.

Why the presence of one or both of these bi-directional devices would limit the power output (presumably disturbing gate-to-source voltage waveform) is not obvious... but is probably the result of having another "long" path from gate-to-board ground, that has RF voltage being induced into it because of the phenomena I mentioned in earlier posts.

I don't know if the tab of the ISXY device is connected to ground (or any of the other terminals), and I don't see any clarification of this in the specification sheet. You could check with an ohm meter. In any event, I would keep the tab insulated from board/chassis ground.

Stu
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« Reply #36 on: January 13, 2015, 12:47:09 PM »

I didn't know they were bidirectional. I'll cut one off.  I built it the same way on my other rig too (using analog drive), so I'll cut that one off too.

I've attached the datasheet for the IXYS.  It's confusing though because it says as a note on page 3 to attach the metal tab on "SI" packages to ground.  I think they meant "CI" packages though because SI's are 8 pin DIPs.

Jon

* IXD_614.pdf (2743.37 KB - downloaded 153 times.)
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« Reply #37 on: January 13, 2015, 01:07:47 PM »

Jon

I would suggest that you not ground the metal tab of the IXYS device.

I would also suggest that, for now, you leave the FET gate-to-source TransSorb(R) overvoltage protection device out. You can add it back in (with short leads, directly between the FET's gate and source) when you have the transmitter working satisfactorily. 

The TransSorb device should have very little effect on the normal behavior of the transmitter... provided its presence is not resulting in excessive RF voltage being induced into the associated wiring loop, or added to a segment of this loop by FET drain current returning to the FET source, via the ground plane.

Stu

I didn't know they were bidirectional. I'll cut one off.  I built it the same way on my other rig too (using analog drive), so I'll cut that one off too.

I've attached the datasheet for the IXYS.  It's confusing though because it says as a note on page 3 to attach the metal tab on "SI" packages to ground.  I think they meant "CI" packages though because SI's are 8 pin DIPs.

Jon
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« Reply #38 on: January 13, 2015, 01:37:51 PM »

Ok, good. That would've required lots of disassembly.

By the way, I did end up getting some 7806's in.  No change in power out.

I've got a plan for the resistor change, twin lead and the 3 ground paths.  I'll also change the TransZorb to G-S leads rather than a distant ground (once I get the transmitter working properly).

Jon
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« Reply #39 on: January 13, 2015, 01:57:43 PM »

Hi Jon,

Am a bit late to this Thread ...

But regarding the three-terminal voltage regulators;

You could jigger the output voltage of a  7805 regulator up in voltage by adding a silicon diode in the Gnd (center pin of a TO-220 package),  and you will have 5.7 volts,  and so on ...

AND,  as you probably know there is the classic LM-317 adjustable positive three terminal regulator,  where two resistors (or even a pot) determine the output voltage,  within the limits of its specs:

http://en.wikipedia.org/wiki/LM317

This is not directly responsive to the topic of this thread,  I realize ... back to regular programming.

Hope that you will be castoff soon   GL,  72  Vic
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« Reply #40 on: January 13, 2015, 02:51:14 PM »

One more observation:  I'm using an IXDD614, which appears only to be good to 2 MHz according to the curves on the datasheet.  An IXDD414 goes past 10 MHz.  Maybe it can't switch fast enough?  Nobody seems to carry the IXDD414's anymore though.

Jon

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« Reply #41 on: January 13, 2015, 03:01:58 PM »

Jon

That could be a limitation... although the rise and fall times for the 614 are actually slightly shorter than the rise and fall times for the 414.

I suggest that you send an E-mail to Steve (WA1QIX) to see if he is still selling 414's from his stash... or if he has a suggestion with respect to the suitability of the 614's for 7MHz operation with a single FET.

Stu
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« Reply #42 on: January 13, 2015, 03:40:11 PM »

One more observation:  I'm using an IXDD614, which appears only to be good to 2 MHz according to the curves on the datasheet.  An IXDD414 goes past 10 MHz.  Maybe it can't switch fast enough?  Nobody seems to carry the IXDD414's anymore though.
Jon  

Jon,

I am not an expert on either the IXDD 414 or the 614,  and in a quick look at the datasheets on each,  looks like they are speced to 1 ot 2 Mhz,  at least on the supply current verses frequency.

The rise and fall times on the 614 APPEAR to be greater,  but on the Claire data for the 614,  the specs cover the complete range of temperature,   and on the older IXYS data for the 414,  the temperature is limited to 25 C.   Am not sure that the 614 is really any worse in frequency capability for a given output C in typical use ...

Must be blind,  but cannot find a maximum frequency for a given supply voltage and load C ...   will look further.


FWIW,  Vic
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« Reply #43 on: January 13, 2015, 04:06:10 PM »

If you look at the Supply Current vs Frequency chart between the two, you can see the difference.  I've attached the datasheets.

Jon

* IXD_614.pdf (2743.37 KB - downloaded 157 times.)
* IXDD414.pdf (346.61 KB - downloaded 143 times.)
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« Reply #44 on: January 13, 2015, 04:27:59 PM »

Jon,

Thanks,  have been looking at the data sheets.  I am not certain that the parts are that different.

Need to get to work,  but  the Tr Tf are not that different with other parameters constant twix the two part numbers.

For what ever reason the 614 is speced at a lower PS current mat on the graphic data,  perhaps this is just to cover small surface mount parts that cannot dissipate as much average power ...

The slope of the supply current vs freq is not much different between the 414 and 614,  and bet that your Gate C is not that large,  realize that you are running at about 7.15 Mhz and so on.  More Later.  GL,  Vic
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« Reply #45 on: January 14, 2015, 05:09:39 AM »

For now, as Stu has suggested, leave the gate transzorbs off !  It just adds capacitance that right now you don't need to deal with.

I think you may need to invest in an oscilloscope  Wink  I am amazed you got this far without one.  You are certainly flying blind.  Without waveforms you really don't know what is going on.

The IXDD614 may or may not work, but the waveform will tell all right away.  Without that, you just don't know.  Things like duty cycle and the like cannot be known without a scope, and I can absolutely tell you that the IXDD414 and probably the IXDD614 *will* change the duty cycle of the input waveform.  I have found the on-time to be longer after going through the IXDD414, meaning it is necessary to over-compensate at the input side in order to get what you want at the output side.  No big deal to do this, but waveform pictures are an absolute necessity.

Regards, Steve
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« Reply #46 on: January 14, 2015, 02:32:55 PM »

I'll bring my transmitter to work tomorrow and post some waveforms.  As it turns out, the scope here is 60 MHz.

Jon
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« Reply #47 on: January 14, 2015, 03:12:45 PM »

I'll bring my transmitter to work tomorrow and post some waveforms.  As it turns out, the scope here is 60 MHz.

Jon

   Jon, a couple of things to consider...

The scope probe should have a quick rise time, and low capacity load. The probe could be 10:1 or 100:1 but NOT 1;1 ratio. The scope may have a scope probe calibrate output displaying a square wave and an approximate amplitude. The probe if anything other than 1:1 should have a compensating adjustment (trimmer capacitor). Adjust for a nice square wave using the scopes calibrate output signal. It is important to use the ground clip on the probe.

Once done, look across a battery, perhaps a 9V battery, and compare against a DVM. It should be close.

These steps are important because skipping these steps might make any data you measure meaningless.

A sine wave at 7.15 Mhz takes about 140 nano-seconds to complete 1 cycle. So put your scope on 20 ns / division. Set the trigger level at around +2 volts, rising edge trigger, auto mode. On the vertical channel, make sure you are DC coupled, and any bandwidth limit is turned OFF.

Remember that most scopes have the ground clip. These clips work there way back to the 120V plug ground pin. So consider that when you hook it to anything. Sparks could fly.

For fast pulse measurements, the ground clip should be very short, like < 1 inch. A spring around the probe ground ring and offset ~3/8"is commonly used.

Getting good data is difficult. Crap for data though is easy, although meaningless.  Lips sealed

Jim
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« Reply #48 on: January 15, 2015, 07:43:20 AM »

These waveforms were taken at 5 volts/div.  The FET appears to be on for a long duty cycle.  I'll post the oscillator output next.

Also to note:  To be able to see most of the large waveforms, I had to move the ground reference off of center screen. 

Jon


* FET drain.JPG (475.6 KB, 1632x1224 - viewed 439 times.)

* FET gate.JPG (450.11 KB, 1632x1224 - viewed 411 times.)

* Filter output.JPG (477.92 KB, 1632x1224 - viewed 433 times.)
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« Reply #49 on: January 15, 2015, 07:45:49 AM »

Oscillator output.

It looks to me like everything is working fine, but I need to reduce the duty cycle.  

Steve: By looking at your VFO schematic, it looks like you do that using an inverting HEX buffer and a NAND chip?

Jon


* Oscillator output.JPG (455.1 KB, 1632x1224 - viewed 427 times.)
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