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Author Topic: 40 meter transmitter  (Read 32727 times)
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ka1tdq
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« on: January 02, 2015, 01:57:27 PM »

I'm almost finished with my single FET, 40 meter CW rig.  This will run off 13.8 vdc and have a power output of 33 watts using class C with digital drive.  The output core has a 1:5 turns ratio with a 2 ohm output impedance for the drain.  The IXDD will also be fed from 13.8 volts, but I don't see that as a problem.

All I have left to do is order the bypass capacitors for the IXDD, and the mica caps for the output network.  I'm using a filter that I found in a 1999 issue of QST.  It uses 3 inductors and has a 2nd order harmonic filter of -60 db. 

I've already tested the crystal oscillator board, and that works fine. 

Jon
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« Reply #1 on: January 03, 2015, 03:13:52 PM »

...and finished.  Instead of getting the 33 watts as I calculated, I'm getting 3.5 watts.  Apparently the IXDD is doing its job and turning the final FET on and off, but the drain voltage must just be too low.  I bet if I put 24 or more volts in there, there'd be a big difference.

I was hoping to make a low voltage rig for the desk without any additional power supplies, but I guess you can't squeeze blood out of 13.8 volts.

**Addition:  I just checked and it's pulling almost 5 amps of current at 13.8 volts on key down.  It's just burning it up in heat. 

Jon
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« Reply #2 on: January 03, 2015, 03:47:51 PM »

Jon

I suspect that something else (not just the low drain-source voltage) is causing the low output power.

Can you post a JPEG of the complete schematic of the output stage, including the output filter and the drain voltage feed circuitry?

As an aside, the photo you posted gives the impression that the gate has a solder bridge shorting it to the drain, and the drain has a wire bridge shorting it to the source.

Some things to check:

What is the average drain current when the unit is operating?

What does the drain voltage waveform look like? You can measure this by placing a simple 10:1 voltage divider between drain and ground ... consisting of a 1000 ohm, 1/2 watt, non inductive resistor in series with a 100 ohm non inductive resistor. This simple voltage divider will roll off the higher frequency harmonics of the drain voltage waveform (because of the parallel capacitance of the 1000 ohm resistor)... but it will give you an idea of what the waveform looks like. The best way to make the 1000 ohm resistor is to put four 270 ohm 1/8 watt resistors in series. This will give the needed dissipation capability... and will minimize the parallel capacitance.

Stu
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« Reply #3 on: January 03, 2015, 04:29:59 PM »

Here's a jpeg of the schematic.  It started out neat on the filter side but then I started getting messy.  

I had another idea as well:  What if the oscillator board isn't putting out a nice 50/50 square wave?  Maybe the final FET is turning on for a short duty cycle or maybe a long duty cycle.  Would that affect efficiency?  I might need to tweak the input going to the IXDD to make sure it gets a logic 0 and logic 1 for equal duration.

**Addition:  And to clarify the photo, there are no solder bridges between the gate-source or the drain-source.  The short wire jumper is going from the IXDD output to the gate of the final.

Jon
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ka1tdq
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« Reply #4 on: January 03, 2015, 04:37:22 PM »

Here's another picture of the IXDD and FET.


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« Reply #5 on: January 03, 2015, 07:21:50 PM »

Nice lash up.
Lesse, 5^1/2 is almost over 2 so that's about right for the final output, if it is 2 ohms.
But is the 2 ohms out right for 12 volts? Or is that for a higher rated Ebb as you've surmised?

Didn't check your filter constants for excessive cutoff but run them again. Perhaps you have a shorted cap or similar too.

Put a 50 ohm non inductive resistor across the output, x off the filter for now and even though rich in harmonics, what do you get for output now?

Just eliminate the watt meter and use a ger. crystal/.o1 cap to ground probe and measure output using E^2/R for wattage.

Warm to the touch? Really 30 watts being dissipated?
Bunch of stuff to try

QST had a similar quad or hex Osc.. Transmitter not too long ago. It put out, what , 2 or 3 watts by itself, no following PA's.  Might be nice to put a simple three pole filter after it too before running into the buffer.

If all else fails simply lash up an electron coupled 2E26 tube Osc. - single stage xmitter, simple PI net out and be done with it.  You'll need slightly higher Ebb though.  Grin
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ka1tdq
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« Reply #6 on: January 03, 2015, 07:33:46 PM »

I did take the output pre-filter (rather crudely using long alligator leads to the coax) and I was getting similar output.  I think the filter is fine. It came from a February 1999 issue of QST.

I was thinking though about the duty cycle and either increasing or decreasing the voltage from the oscillator chip. It is easier to decrease voltage levels by putting a pot in line to the IXDD.

As I turned the trimmer off max, output gradually decreased to zero watts. I think I need a higher max voltage from the oscillator to change the duty cycle.  I just ordered a 7806 voltage regulator. This is the max voltage you can go with the chip (actually 6.5 volts).

I don't have a scope either. My only access to one is at work, and 75 meter waveforms was pushing that to its limits... This is 40 meters.

Sent from my iPhone

Jon
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« Reply #7 on: January 04, 2015, 11:37:45 AM »

Jon

It is going to be difficult to troubleshoot this transmitter without an oscilloscope with at least a 20MHz 3dB bandwidth (preferably 7 x 7MHz = approximately 50MHz)

I suggest that you focus on the gate drive circuitry... and, in particular, on the physical layout.

The output waveform of the IXYS driver (volts v. time) is a rectangular wave of some duty cycle. For the moment, let's assume that is a square wave (50% duty cycle).

A square wave can be represented (Fourier series) as a DC (average value) plus a sine wave at the fundamental frequency (7 MHz), plus sine waves at odd multiples of the fundamental frequency.

The input capacitance of the FET is around 2700pF, which corresponds to an impedance of -j8.4 ohms at 7MHz.

With this low input impedance, it is important that the wiring (transmission line) between the IXYS chip and the FET not introduce an effective series inductance of more than around 0.2uH. Otherwise, the fundamental frequency component of the gate-to-source voltage will be attenuated by the voltage drop across the impedance of the series inductance. If the fundamental frequency component of the gate-to-source voltage is attenuated too much... all you will be left with is the DC (average value) component... which will produce DC from drain-to-source, but no RF.

The transmission line you are using between the IXYS chip and the FET consists of a relatively long wire between the output of the IXYS chip and the gate of the FET (far above the nearest ground)... with the ground return, from the FET's source back to the ground side output of the IXYS chip via the chassis. This won't work at these low impedance levels.

I would suggest that you try the following

Plan A:

Run a twisted pair of wires directly from the output of the IXYS chip (one side connected to the ground pin of the IXYS chip) to the gate and source pins of the FET.
This will probably result in more RF output... because the fundamental frequency sine wave component of the gate-to-source voltage will be higher.

Plan B.

If plan A doesn't produce a sufficient improvement, relocate the IXYS chip closer to the FET. [In my single FET class E transmitter, I placed the IXYS chip on top of the FET... and used a single screw to attach the piggyback pair to the heat sink.]

Separately from the above:

Make sure that the capacitor across the IXYS chip, from the B+ lead to the ground lead (using short leads), is of at least the recommended value... so that the IXYS chip has a "stiff" B+ supply. Without this (charge reservoir) capacitor, from B+ to ground, the IXYS chip cannot produce the necessary current swing to drive the FET.

Stu  

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ka1tdq
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« Reply #8 on: January 04, 2015, 01:29:18 PM »

I will try the twisted pair idea later on this evening when I get home.

As for the series inductance and the long lead, using the 7806 instead of the 7805 will help alleviate the voltage attenuation.

I think the wire lead to the gate is barking up the right tree. I replaced that lead earlier this morning with a slightly smaller gauge and slightly shorter length wire, and output went up slightly to 3.9 watts.

I have a good spool of twisted wire that I picked up at a thrift store for $1.  Yay Goodwill.

Jon
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« Reply #9 on: January 04, 2015, 01:56:25 PM »

Jon

Going from the 7805 to the 7806 may not be helpful.

The issue is whether the combination of the "transmission line" between the IXYS chip and the FET, and the FET's gate-source input capacitance is acting like a low pass filter (because of the series inductance of the "transmission line"). The 7MHz and higher frequency components of the IXYS output voltage waveform are being rolled off... and, essentially, all that is left, across the gate-to-source input of the FET, is the average value of the IXYS output square wave. The small amounts of 7MHz and higher frequency components that pass through this low pass filter are what is producing a small amount of 7MHz drain current swing at the output of the FET. The average value of the square wave IXYS output voltage passes, unattenuated, through this low pass filter... and (after subtracting the FET's gate-to-source threshold voltage) produces the 5A average drain current that you are measuring.

So, the FET is spending most of its time at 5A of average drain current, with a little bit of 7MHz ripple in the drain current waveform.

More B+ voltage on the IXYS chip will increase the output, but will not change the ratio of DC (the average value of the gate-to-source voltage) to 7MHz and higher frequency components. More B+ on the IXYS chip might even make things worse (more average FET drain current, but less 7MHz swing).

Stu
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« Reply #10 on: January 04, 2015, 02:36:32 PM »

I see. I had it in my head that you were talking about the long wire between the oscillator chip and the input to the IXYS. So, wow... That little one inch wire between the IXYS and the FET gate is acting like a low pass filter. 

I'll change that one piece of wire to a twisted pair like you said.

Separately though, would changing the 7805 to a 7806 on the crystal oscillator chip make a difference? I don't know what the output waveform of the oscillator looks like. It could be on 75% and off 25% (or whatever percentages) causing the IXYS to be on and off accordingly for the same percentages.  If it is off, and I will never know without a scope, it could also be wreaking havoc.

I did do that test though. I put a 100k pot on my the output of the oscillator to ground. I fed the IXYS input from the wiper.

At the top of the po lt output was full at 3.5 watts. As I gradually turned down the wiper, output power gradually went down as well to ultimately zero output.

It seems to me that if I could go a little over 5 volts output from the oscillator could increase power output, for whatever reason.

Jon
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« Reply #11 on: January 04, 2015, 03:06:58 PM »

Jon

Use a twisted pair between the oscillator and the IXYS chip, as well as between the IXYS chip and the FET.

The wire between the IXYS chip and the FET may not be very long... but the return path, via the chassis, is a problem. You want equal and opposite currents flowing in the two, closely spaced wires of the twisted pair, in order to minimize the magnetic energy stored and removed in the transmission line in each half cycle of the 7MHz square wave... and thus to minimize the series inductance of the link between the IXYS chip and the FET. The existing path is a loop (IXYS=>to single wire=>FET=>chassis=>IXYS) that encloses enough area to result in too much magnetic energy being stored and removed on each half cycle of the 7MHz square wave. The more stored and removed magnetic energy on each half cycle of the square wave... the larger the peak voltage drop around the wire portions of the loop (more impedance).

Building up the energy that is stored in the magnetic field each quarter cycle (and then removing it in the next quarter cycle) implies that power is flowing into and out of the magnetic field. The power flowing into the magnetic field is the product of the current flowing around the loop and the sum of the voltages across each of the wire legs that make up the loop. The voltage across each wire leg is L x di/dt, where L is the inductance of that wire leg, and di/dt is the rate of change of the current flowing through that leg. Therefore: more peak stored magnetic energy => more inductance.

Stu
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« Reply #12 on: January 04, 2015, 03:08:12 PM »

oops...someone replied before me,

  At my workplace where we repair commercial 13.56 Mhz RF Amplifiers (3KW), I had to devise a good and repeatable way to measure the RF FET gate excitation. A scope with a 10 ns / division sweep (non magnified) is needed since one wave at 13.56 Mhz occurs in about 74 ns. The scope is digital at 1G-Sample/sec, and 100 Mhz vertical bandwidth. This scope is barely up to the task. The probe is 100X compensated to 100 Mhz (10X would be better). I use a little spring loaded ground clip that has only 3/8" distance to it such that I can probe from FET case (Source) to gate. The scope probe cable made a difference which way it flopped, so I added a clamp on ferrite bead to make a 3 turn common mode choke that is about 12" away from the probe handle. The results are now very repeatable, and consistent.

  The OEM FET's (2 in parallel) present 5 nf capacity each. The driver is RF sine wave, and about 9V peak is all we can get. The RF efficiency peaks as the drive is reduced to the threshold where the FET drain voltage starts to climb when the FET is conducting (increased RDS ON).

I suppose that with pulse type drive, the pulse width should be slightly less than a half wave (maybe 35 ns at 13.56 Mhz). When the drive pulse is too wide, the gate threshold is made while the FET drain is coming down but still high, and this causes a dissipative condition that the class E guys call, I think..."Back Porching".

Jim
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« Reply #13 on: January 04, 2015, 07:26:08 PM »

I put twisted pairs in between both, but no change in power output.  I've attached a photo from a different angle to better show the connections.  

** After that I tried replacing the .47uF capacitors with shorter leads of .047uF (I know, the reactance value is higher, but I wanted to try something) and power went even lower to 2 watts.

I guess rebuilding with the IXYS on the same stud as the FET is the next step.

Jon
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« Reply #14 on: January 04, 2015, 10:18:22 PM »

Jon

Without an oscilloscope you are groping around in the dark on this.

Stu
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« Reply #15 on: January 04, 2015, 10:45:46 PM »

Just for ha-ha's, I'm going to put the 7806 in to satisfy my curiosity.  That'll come in the mail in a couple days.  If that does nothing then I'll round up a scope with sufficient speed.

I need to see what's coming out of all 3 stages:  the oscillator, IXYS and FET.
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« Reply #16 on: January 05, 2015, 11:53:31 AM »

Jon

I was looking at your posted schematic.

Of note: pin 10 of the inverter chip is supposed to be connected to ground. Perhaps this is just an error in the schematic v. the actual oscillator wiring.

Have you listened for the output of the transmitter with a receiver... to verify that the oscillator is actually oscillating at the crystal frequency?

Even if the oscillator is oscillating at 7Mhz, it may not be producing a 7MHz output signal that looks anything like a square wave toggling between logical high voltage and logical low voltage. Instead, it may be producing an output signal that is a DC plus a small amount of 7MHz ripple. The reason it might be doing this is because the inverter is not fast enough (although 7ns of propagation delay is much less than the time to complete a quarter cycle of a 7MHz square wave). Alternatively, this might be a consequence of the details of the specific oscillator circuit design you are using.

You might want to measure the DC voltage at the output of the oscillator... with a multimeter. If the oscillator is toggling between logical high and logical low... then the DC output voltage will be: the logical high voltage x the duty cycle.

Stu
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« Reply #17 on: January 05, 2015, 02:05:06 PM »

The schematic I drew up looks pretty nasty.  I did ground pin #10.  I've attached a photo of the QST article that I got the schematic from.  I used it minus the output network to the antenna.  Of note:  the schematic calls for 6 volts DC and not 5 like I used.

I did listen to the oscillator board by itself on a receiver and it sounds good.  I also listened to the transmitter (all 3.5 watts) and it too keys fine on a receiver.  

I will do the multimeter test today after work to see what I get.

Jon


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« Reply #18 on: January 05, 2015, 08:14:02 PM »

Unkeyed, I get 0.0 volts.  Keyed, I get 2.3 vdc.  

I also volt-metered the gate of the FET.  I'm only getting 2.6 vdc there during key down. 

Jon
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« Reply #19 on: January 05, 2015, 11:19:41 PM »

Jon

Well that's a good sign. It doesn't imply that the output of the crystal oscillator is toggling between 0V and 5V with a 50% duty cycle... but that is what you would expect the DC (i.e. average) output voltage to be if it is toggling between 0V and 5V with approximately a 50% duty cycle.

As a next thing to try... measure the DC (average) voltage, key open and key closed, at the output of the IXYS driver.

Stu
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« Reply #20 on: January 06, 2015, 07:01:17 AM »

Key up out of the IXYS is 0 volts key up, and 2.6 volts key down.

Jon
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« Reply #21 on: January 06, 2015, 10:29:03 AM »

Jon

With 13.8V B+ on the IXYS driver, it should be trying to toggle its output voltage between VCL=0.025V and VCH= 13.8V-0.025V. Based on Steve's (WA1QIX) web site picture of the 7MHz output waveform (actually the FET gate-to-source waveform), it should have a peak value of more than 12V. The DC (average) value of the output voltage should be around 6.9V.

http://ixdev.ixys.com/DataSheet/99061.pdf

http://www.classeradio.com/driver.htm

Your measured DC output voltage (2.6V) suggests that the IXYS device is not putting out a 50% duty cycle waveform, toggling between VCL and VCH.

Check to see what the DC value of the voltage is between pin 1 (B+) and pin 3 (ground)... both on key up and key down.

If this voltage is significantly lower on key down, then the 13.8V supply has too much series resistance and/or you have not installed enough charge reservoir capacitance between pin 1 and pin 3. In fact, I cannot see this capacitor between pin 1 and pin 3 in your photos.

From the IXYS data sheet for the IXDD414:

SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXDD414
must be able to draw this 5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the
power supply at the driver with a capacitance value that is a
magnitude larger than the load capacitance.
Usually, this
would be achieved by placing two different types of bypassing
capacitors, with complementary impedance curves, very close
to the driver itself. (These capacitors should be carefully
selected, low inductance, low resistance, high-pulse current service
capacitors). Lead lengths may radiate at high frequency
due to inductance, so care should be taken to keep the lengths
of the leads between these bypass capacitors and the IXDD414
to an absolute minimum
.

The FET load capacitance is around 2700pf. Therefore you need a charge reservoir capacitor with a value of around 27000pF = .027uF (or more). A 0.02uF capacitor would probably be okay.

Stu


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« Reply #22 on: January 06, 2015, 11:06:21 AM »

I tried another experiment after I found out that the FET gate was only getting an average value of 2.6 vdc (again, not sure exactly the duty cycle %). I fed the gate directly from the oscillator.  The oscillator is doing 2.5 vdc-ish so I should be getting similar output. 

I got zero.  That tells me that the 50% duty cycle, 5 volt peak waveform coming from the oscillator wasn't enough to drive the FET.  Also, it does tell me that the IXYS must be putting out 13.8 vdc peaks (albeit at a greatly reduced duty cycle) to actually turn the FET on and off to get some output, at least.

So...

I've butchered this poor IXYS chip, soldering - resoldering and all.  I may have even zorched it testing with wire leads since now the rig only puts out 1.5 watts.  I've ordered a couple more and I'm going to rebuild that section completely.  I'll use the new value of capacitor that you suggest for the bypassing, beefed up DC wiring and shorter leads throughout. 

Jon
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« Reply #23 on: January 06, 2015, 02:38:53 PM »

Jon

Clarifications:

It takes between 3V and 5V of gate-to-source voltage to turn on the 11N90 (see the 11N90 data sheet: VGS(th)=Gate Threshold Voltage). A 0V-to-12V G-S voltage swing is desirable for preventing parasitic oscillations that can occur when the G-S voltage is too close to the threshold value for too long a time. Given that there is 5A of average drain current, but only a few watts of RF output... I suspect that (in the present configuration) the IXYS driver is keeping the FET G-S voltage above threshold most of the time. If the RF load seen from drain-to-source is 2 ohms... then 4 watts of RF output would correspond to about 4A of peak-to-peak swing of the 7MHz sinusoidal component of the drain current.


https://www.fairchildsemi.com/datasheets/FQ/FQA11N90C_F109.pdf

The oscillator cannot directly drive the low impedance looking into the FET (2700pF of gate-source capacitance)... so it is not driving the G-S voltage to the 5V level that it (apparently) produces when it looks into the 100 ohm load you have at the input of the IXYS driver.

Try tacking a 0.02uF or 0.047uF capacitor directly between pins 1 and 3 of the IXYS driver before replacing the IXYS driver or redoing the physical layout.

Stu
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« Reply #24 on: January 07, 2015, 03:36:48 PM »

I put the .047 capacitor between pins 1 and 3 last night but I got nothing for power output.  The oscillator is still working but I get nothing out of the IXYS... it must've gone zorch with all the tweaking.

I'm still waiting for all the new parts to come in, and I'm going to completely re-do the IXYS. 

I'll drill a hole to mount it closer to the FET and reduce the ground lead length by mounting a 90 degree piece of copper directly beneath the IXYS.  It'll then be easier to solder the bypass capacitors directly to the 3rd pin.

And again, I'll use solid 14 gauge wire to supply the 13.8 vdc to the IXYS instead of the thin stuff I have now.

Not relevant to troubleshooting, but I'm also replacing the small ceramic disc capacitors that are in the filter.  I've ordered 1kv micas.

Things all should be in by the weekend, so I'll poster after I get it all done.

Jon

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