Key difference between class D & E

[W1FVB]

....
With true class D, the RF voltage peaks do not, in theory, rise as high as they do in class E - *HOWEVER* this is only true for a properly terminated RF amplifier.  If the load is bad, the voltage, particularly for a single ended class D RF stage, will rise to the same or higher levels than you will get in Class E.

Thanks for the reminder, I've just added protection diodes to this circuit
a 1.5KE18CA diode on the gate and a 1.5KE180CA on the drain.

Frits W1FVB

[ND9B]

OK, I understand the whole idea behind class D/E is efficiency, and I assume class E is more efficient than class D, or there would be no point to class E. But, what are the real numbers? 

-Inquiring minds want to know.-

ND9B

[steve_qix]

OK, I understand the whole idea behind class D/E is efficiency, and I assume class E is more efficient than class D, or there would be no point to class E. But, what are the real numbers? 

-Inquiring minds want to know.-

ND9B

Well, there are lots of reasons to use one over the other.

Class D works well if:

You have a known, constant, resistive load for the transmitter to work into
It is not necessary to tune the transmitter (to vary the RF amplifier current, etc.)
The operating frequency is low enough for the devices to function properly in the mode
The operating frequency does not vary too far from the design center frequency
There is a good physical layout available
Stray inductances in the output are not too high

Class E is favored if:

The load the transmitter sees varies or is reactive
The ability to tune the transmitter or adjust the current is desired
The operating frequency is higher than the devices can efficiently switch
The operating frequency varies over a wide range
There is stray inductance in the output or the physical layout

Anyway, there are some differences.

Regards,

Steve

[W1VD]

Agree with Steve's comments above except for a couple minor points ...

Current-mode Class D transmitters have been built for frequencies to at least 1 GHz

Current-mode Class D decks are readily built to cover an entire band - more if willing to bandswitch.

(One should specify the Class D mode of operation - half or full bridge, voltage-mode Class D, current-mode Class D, etc since various modes exhibit different characteristics.)

As for efficiency, theoretically Class D has a slight edge over E ... but in reality they end up pretty close. The current-mode decks I've built for 160 and 80 meters run mid 90s and 40 meters low 90s.

[steve_qix]

That's right!  Current mode class D is quite a bit better than voltage mode as the freq goes up!  Jay is definitely the expert here.  It might be worth giving an explanation of current mode class D as opposed to voltage mode 

Regards,

Steve

[W1VD]

The difference between voltage-mode Class D (VMCD) and current-mode Class D (CMCD) can be seen in the drawings below.

At the left is voltage-mode Class D ... which gets its name because the amplifier is fed from a voltage source. Vdd is assumed to have a low impedance at the operating frequency. This results in a drain waveform where the voltage approximates a square wave and the current a sine wave.

At the right is current mode Class D ... similarly named because the amplifier is fed from a current source ... approximated by feeding Vdd through rf choke(s). (In the top right drawing replace the current source symbols with rf chokes.) This results in a drain waveform where the voltage approximates a sine wave and the current a square wave.

With increasing frequency of operation the FET parasitic capacitance has an increasing affect on circuit operation. In voltage-mode Class D it becomes impossible to ensure zero voltage switching (ZVS) - a prerequisite for high efficiency whereas current-mode Class D can.

Class E transmitters are adjusted for ZVS as a byproduct of obtaining the 'classic' drain waveform ... or by using Steve's clever efficiency meter. 

http://www.w1vd.com/VMCDCMCD.jpg 

[WA1GFZ]

Current mode class D. The series inductor also helps when FET timing is such that if the timing is ever off to a point when both FETs are on at the same time the current transient is limiter by E=L di/dt. So L is a time delay for a current transient.
This method is used in push pull  switching power supplies to increase efficiency when both phases have slight overlap to get ZVSing.
So just like class e you are playing a timing game to get the advantage of ZVS.
class e the shunt cap, class d current mode the series inductor.
Class D voltage mode gate timing is critical to avoid big boom....