The AM Forum

I'm almost finished with my single FET, 40 meter CW rig.  This will run off 13.8 vdc and have a power output of 33 watts using class C with digital drive.  The output core has a 1:5 turns ratio with a 2 ohm output impedance for the drain.  The IXDD will also be fed from 13.8 volts, but I don't see that as a problem.

All I have left to do is order the bypass capacitors for the IXDD, and the mica caps for the output network.  I'm using a filter that I found in a 1999 issue of QST.  It uses 3 inductors and has a 2nd order harmonic filter of -60 db. 

I've already tested the crystal oscillator board, and that works fine. 

Jon
KA1TDQ

...and finished.  Instead of getting the 33 watts as I calculated, I'm getting 3.5 watts.  Apparently the IXDD is doing its job and turning the final FET on and off, but the drain voltage must just be too low.  I bet if I put 24 or more volts in there, there'd be a big difference.

I was hoping to make a low voltage rig for the desk without any additional power supplies, but I guess you can't squeeze blood out of 13.8 volts.

**Addition:  I just checked and it's pulling almost 5 amps of current at 13.8 volts on key down.  It's just burning it up in heat. 

Jon
KA1TDQ

Jon

I suspect that something else (not just the low drain-source voltage) is causing the low output power.

Can you post a JPEG of the complete schematic of the output stage, including the output filter and the drain voltage feed circuitry?

As an aside, the photo you posted gives the impression that the gate has a solder bridge shorting it to the drain, and the drain has a wire bridge shorting it to the source.

Some things to check:

What is the average drain current when the unit is operating?

What does the drain voltage waveform look like? You can measure this by placing a simple 10:1 voltage divider between drain and ground ... consisting of a 1000 ohm, 1/2 watt, non inductive resistor in series with a 100 ohm non inductive resistor. This simple voltage divider will roll off the higher frequency harmonics of the drain voltage waveform (because of the parallel capacitance of the 1000 ohm resistor)... but it will give you an idea of what the waveform looks like. The best way to make the 1000 ohm resistor is to put four 270 ohm 1/8 watt resistors in series. This will give the needed dissipation capability... and will minimize the parallel capacitance.

Stu

Here's a jpeg of the schematic.  It started out neat on the filter side but then I started getting messy.  

I had another idea as well:  What if the oscillator board isn't putting out a nice 50/50 square wave?  Maybe the final FET is turning on for a short duty cycle or maybe a long duty cycle.  Would that affect efficiency?  I might need to tweak the input going to the IXDD to make sure it gets a logic 0 and logic 1 for equal duration.

**Addition:  And to clarify the photo, there are no solder bridges between the gate-source or the drain-source.  The short wire jumper is going from the IXDD output to the gate of the final.

Jon
KA1TDQ

Here's another picture of the IXDD and FET.

Nice lash up.
Lesse, 5^1/2 is almost over 2 so that's about right for the final output, if it is 2 ohms.
But is the 2 ohms out right for 12 volts? Or is that for a higher rated Ebb as you've surmised?

Didn't check your filter constants for excessive cutoff but run them again. Perhaps you have a shorted cap or similar too.

Put a 50 ohm non inductive resistor across the output, x off the filter for now and even though rich in harmonics, what do you get for output now?

Just eliminate the watt meter and use a ger. crystal/.o1 cap to ground probe and measure output using E^2/R for wattage.

Warm to the touch? Really 30 watts being dissipated?
Bunch of stuff to try

QST had a similar quad or hex Osc.. Transmitter not too long ago. It put out, what , 2 or 3 watts by itself, no following PA's.  Might be nice to put a simple three pole filter after it too before running into the buffer.

If all else fails simply lash up an electron coupled 2E26 tube Osc. - single stage xmitter, simple PI net out and be done with it.  You'll need slightly higher Ebb though.  ;D

I did take the output pre-filter (rather crudely using long alligator leads to the coax) and I was getting similar output.  I think the filter is fine. It came from a February 1999 issue of QST.

I was thinking though about the duty cycle and either increasing or decreasing the voltage from the oscillator chip. It is easier to decrease voltage levels by putting a pot in line to the IXDD.

As I turned the trimmer off max, output gradually decreased to zero watts. I think I need a higher max voltage from the oscillator to change the duty cycle.  I just ordered a 7806 voltage regulator. This is the max voltage you can go with the chip (actually 6.5 volts).

I don't have a scope either. My only access to one is at work, and 75 meter waveforms was pushing that to its limits... This is 40 meters.

Sent from my iPhone

Jon
KA1TDQ

Jon

It is going to be difficult to troubleshoot this transmitter without an oscilloscope with at least a 20MHz 3dB bandwidth (preferably 7 x 7MHz = approximately 50MHz)

I suggest that you focus on the gate drive circuitry... and, in particular, on the physical layout.

The output waveform of the IXYS driver (volts v. time) is a rectangular wave of some duty cycle. For the moment, let's assume that is a square wave (50% duty cycle).

A square wave can be represented (Fourier series) as a DC (average value) plus a sine wave at the fundamental frequency (7 MHz), plus sine waves at odd multiples of the fundamental frequency.

The input capacitance of the FET is around 2700pF, which corresponds to an impedance of -j8.4 ohms at 7MHz.

With this low input impedance, it is important that the wiring (transmission line) between the IXYS chip and the FET not introduce an effective series inductance of more than around 0.2uH. Otherwise, the fundamental frequency component of the gate-to-source voltage will be attenuated by the voltage drop across the impedance of the series inductance. If the fundamental frequency component of the gate-to-source voltage is attenuated too much... all you will be left with is the DC (average value) component... which will produce DC from drain-to-source, but no RF.

The transmission line you are using between the IXYS chip and the FET consists of a relatively long wire between the output of the IXYS chip and the gate of the FET (far above the nearest ground)... with the ground return, from the FET's source back to the ground side output of the IXYS chip via the chassis. This won't work at these low impedance levels.

I would suggest that you try the following

Plan A:

Run a twisted pair of wires directly from the output of the IXYS chip (one side connected to the ground pin of the IXYS chip) to the gate and source pins of the FET.
This will probably result in more RF output... because the fundamental frequency sine wave component of the gate-to-source voltage will be higher.

Plan B.

If plan A doesn't produce a sufficient improvement, relocate the IXYS chip closer to the FET. [In my single FET class E transmitter, I placed the IXYS chip on top of the FET... and used a single screw to attach the piggyback pair to the heat sink.]

Separately from the above:

Make sure that the capacitor across the IXYS chip, from the B+ lead to the ground lead (using short leads), is of at least the recommended value... so that the IXYS chip has a "stiff" B+ supply. Without this (charge reservoir) capacitor, from B+ to ground, the IXYS chip cannot produce the necessary current swing to drive the FET.

Stu  

I will try the twisted pair idea later on this evening when I get home.

As for the series inductance and the long lead, using the 7806 instead of the 7805 will help alleviate the voltage attenuation.

I think the wire lead to the gate is barking up the right tree. I replaced that lead earlier this morning with a slightly smaller gauge and slightly shorter length wire, and output went up slightly to 3.9 watts.

I have a good spool of twisted wire that I picked up at a thrift store for $1.  Yay Goodwill.

Jon
KA1TDQ

Jon

Going from the 7805 to the 7806 may not be helpful.

The issue is whether the combination of the "transmission line" between the IXYS chip and the FET, and the FET's gate-source input capacitance is acting like a low pass filter (because of the series inductance of the "transmission line"). The 7MHz and higher frequency components of the IXYS output voltage waveform are being rolled off... and, essentially, all that is left, across the gate-to-source input of the FET, is the average value of the IXYS output square wave. The small amounts of 7MHz and higher frequency components that pass through this low pass filter are what is producing a small amount of 7MHz drain current swing at the output of the FET. The average value of the square wave IXYS output voltage passes, unattenuated, through this low pass filter... and (after subtracting the FET's gate-to-source threshold voltage) produces the 5A average drain current that you are measuring.

So, the FET is spending most of its time at 5A of average drain current, with a little bit of 7MHz ripple in the drain current waveform.

More B+ voltage on the IXYS chip will increase the output, but will not change the ratio of DC (the average value of the gate-to-source voltage) to 7MHz and higher frequency components. More B+ on the IXYS chip might even make things worse (more average FET drain current, but less 7MHz swing).

Stu

I see. I had it in my head that you were talking about the long wire between the oscillator chip and the input to the IXYS. So, wow... That little one inch wire between the IXYS and the FET gate is acting like a low pass filter. 

I'll change that one piece of wire to a twisted pair like you said.

Separately though, would changing the 7805 to a 7806 on the crystal oscillator chip make a difference? I don't know what the output waveform of the oscillator looks like. It could be on 75% and off 25% (or whatever percentages) causing the IXYS to be on and off accordingly for the same percentages.  If it is off, and I will never know without a scope, it could also be wreaking havoc.

I did do that test though. I put a 100k pot on my the output of the oscillator to ground. I fed the IXYS input from the wiper.

At the top of the po lt output was full at 3.5 watts. As I gradually turned down the wiper, output power gradually went down as well to ultimately zero output.

It seems to me that if I could go a little over 5 volts output from the oscillator could increase power output, for whatever reason.

Jon

Jon

Use a twisted pair between the oscillator and the IXYS chip, as well as between the IXYS chip and the FET.

The wire between the IXYS chip and the FET may not be very long... but the return path, via the chassis, is a problem. You want equal and opposite currents flowing in the two, closely spaced wires of the twisted pair, in order to minimize the magnetic energy stored and removed in the transmission line in each half cycle of the 7MHz square wave... and thus to minimize the series inductance of the link between the IXYS chip and the FET. The existing path is a loop (IXYS=>to single wire=>FET=>chassis=>IXYS) that encloses enough area to result in too much magnetic energy being stored and removed on each half cycle of the 7MHz square wave. The more stored and removed magnetic energy on each half cycle of the square wave... the larger the peak voltage drop around the wire portions of the loop (more impedance).

Building up the energy that is stored in the magnetic field each quarter cycle (and then removing it in the next quarter cycle) implies that power is flowing into and out of the magnetic field. The power flowing into the magnetic field is the product of the current flowing around the loop and the sum of the voltages across each of the wire legs that make up the loop. The voltage across each wire leg is L x di/dt, where L is the inductance of that wire leg, and di/dt is the rate of change of the current flowing through that leg. Therefore: more peak stored magnetic energy => more inductance.

Stu

oops...someone replied before me,

  At my workplace where we repair commercial 13.56 Mhz RF Amplifiers (3KW), I had to devise a good and repeatable way to measure the RF FET gate excitation. A scope with a 10 ns / division sweep (non magnified) is needed since one wave at 13.56 Mhz occurs in about 74 ns. The scope is digital at 1G-Sample/sec, and 100 Mhz vertical bandwidth. This scope is barely up to the task. The probe is 100X compensated to 100 Mhz (10X would be better). I use a little spring loaded ground clip that has only 3/8" distance to it such that I can probe from FET case (Source) to gate. The scope probe cable made a difference which way it flopped, so I added a clamp on ferrite bead to make a 3 turn common mode choke that is about 12" away from the probe handle. The results are now very repeatable, and consistent.

  The OEM FET's (2 in parallel) present 5 nf capacity each. The driver is RF sine wave, and about 9V peak is all we can get. The RF efficiency peaks as the drive is reduced to the threshold where the FET drain voltage starts to climb when the FET is conducting (increased RDS ON).

I suppose that with pulse type drive, the pulse width should be slightly less than a half wave (maybe 35 ns at 13.56 Mhz). When the drive pulse is too wide, the gate threshold is made while the FET drain is coming down but still high, and this causes a dissipative condition that the class E guys call, I think..."Back Porching".

Jim
Wd5JKO

I put twisted pairs in between both, but no change in power output.  I've attached a photo from a different angle to better show the connections.  

** After that I tried replacing the .47uF capacitors with shorter leads of .047uF (I know, the reactance value is higher, but I wanted to try something) and power went even lower to 2 watts.

I guess rebuilding with the IXYS on the same stud as the FET is the next step.

Jon
KA1TDQ

Jon

Without an oscilloscope you are groping around in the dark on this.

Stu

Just for ha-ha's, I'm going to put the 7806 in to satisfy my curiosity.  That'll come in the mail in a couple days.  If that does nothing then I'll round up a scope with sufficient speed.

I need to see what's coming out of all 3 stages:  the oscillator, IXYS and FET.

Jon

I was looking at your posted schematic.

Of note: pin 10 of the inverter chip is supposed to be connected to ground. Perhaps this is just an error in the schematic v. the actual oscillator wiring.

Have you listened for the output of the transmitter with a receiver... to verify that the oscillator is actually oscillating at the crystal frequency?

Even if the oscillator is oscillating at 7Mhz, it may not be producing a 7MHz output signal that looks anything like a square wave toggling between logical high voltage and logical low voltage. Instead, it may be producing an output signal that is a DC plus a small amount of 7MHz ripple. The reason it might be doing this is because the inverter is not fast enough (although 7ns of propagation delay is much less than the time to complete a quarter cycle of a 7MHz square wave). Alternatively, this might be a consequence of the details of the specific oscillator circuit design you are using.

You might want to measure the DC voltage at the output of the oscillator... with a multimeter. If the oscillator is toggling between logical high and logical low... then the DC output voltage will be: the logical high voltage x the duty cycle.

Stu

The schematic I drew up looks pretty nasty.  I did ground pin #10.  I've attached a photo of the QST article that I got the schematic from.  I used it minus the output network to the antenna.  Of note:  the schematic calls for 6 volts DC and not 5 like I used.

I did listen to the oscillator board by itself on a receiver and it sounds good.  I also listened to the transmitter (all 3.5 watts) and it too keys fine on a receiver.  

I will do the multimeter test today after work to see what I get.

Jon

Unkeyed, I get 0.0 volts.  Keyed, I get 2.3 vdc.  

I also volt-metered the gate of the FET.  I'm only getting 2.6 vdc there during key down. 

Jon

Jon

Well that's a good sign. It doesn't imply that the output of the crystal oscillator is toggling between 0V and 5V with a 50% duty cycle... but that is what you would expect the DC (i.e. average) output voltage to be if it is toggling between 0V and 5V with approximately a 50% duty cycle.

As a next thing to try... measure the DC (average) voltage, key open and key closed, at the output of the IXYS driver.

Stu

Key up out of the IXYS is 0 volts key up, and 2.6 volts key down.

Jon

Jon

With 13.8V B+ on the IXYS driver, it should be trying to toggle its output voltage between VCL=0.025V and VCH= 13.8V-0.025V. Based on Steve's (WA1QIX) web site picture of the 7MHz output waveform (actually the FET gate-to-source waveform), it should have a peak value of more than 12V. The DC (average) value of the output voltage should be around 6.9V.

http://ixdev.ixys.com/DataSheet/99061.pdf

http://www.classeradio.com/driver.htm

Your measured DC output voltage (2.6V) suggests that the IXYS device is not putting out a 50% duty cycle waveform, toggling between VCL and VCH.

Check to see what the DC value of the voltage is between pin 1 (B+) and pin 3 (ground)... both on key up and key down.

If this voltage is significantly lower on key down, then the 13.8V supply has too much series resistance and/or you have not installed enough charge reservoir capacitance between pin 1 and pin 3. In fact, I cannot see this capacitor between pin 1 and pin 3 in your photos.

From the IXYS data sheet for the IXDD414:

SUPPLY BYPASSING
In order for our design to turn the load on properly, the IXDD414
must be able to draw this 5A of current from the power supply
in the 25ns. This means that there must be very low impedance
between the driver and the power supply. The most common
method of achieving this low impedance is to bypass the
power supply at the driver with a capacitance value that is a
magnitude larger than the load capacitance. Usually, this
would be achieved by placing two different types of bypassing
capacitors, with complementary impedance curves, very close
to the driver itself. (These capacitors should be carefully
selected, low inductance, low resistance, high-pulse current service
capacitors). Lead lengths may radiate at high frequency
due to inductance, so care should be taken to keep the lengths
of the leads between these bypass capacitors and the IXDD414
to an absolute minimum.

The FET load capacitance is around 2700pf. Therefore you need a charge reservoir capacitor with a value of around 27000pF = .027uF (or more). A 0.02uF capacitor would probably be okay.

Stu

I tried another experiment after I found out that the FET gate was only getting an average value of 2.6 vdc (again, not sure exactly the duty cycle %). I fed the gate directly from the oscillator.  The oscillator is doing 2.5 vdc-ish so I should be getting similar output. 

I got zero.  That tells me that the 50% duty cycle, 5 volt peak waveform coming from the oscillator wasn't enough to drive the FET.  Also, it does tell me that the IXYS must be putting out 13.8 vdc peaks (albeit at a greatly reduced duty cycle) to actually turn the FET on and off to get some output, at least.

So...

I've butchered this poor IXYS chip, soldering - resoldering and all.  I may have even zorched it testing with wire leads since now the rig only puts out 1.5 watts.  I've ordered a couple more and I'm going to rebuild that section completely.  I'll use the new value of capacitor that you suggest for the bypassing, beefed up DC wiring and shorter leads throughout. 

Jon

Jon

Clarifications:

It takes between 3V and 5V of gate-to-source voltage to turn on the 11N90 (see the 11N90 data sheet: V_GS(th)=Gate Threshold Voltage). A 0V-to-12V G-S voltage swing is desirable for preventing parasitic oscillations that can occur when the G-S voltage is too close to the threshold value for too long a time. Given that there is 5A of average drain current, but only a few watts of RF output... I suspect that (in the present configuration) the IXYS driver is keeping the FET G-S voltage above threshold most of the time. If the RF load seen from drain-to-source is 2 ohms... then 4 watts of RF output would correspond to about 4A of peak-to-peak swing of the 7MHz sinusoidal component of the drain current.


https://www.fairchildsemi.com/datasheets/FQ/FQA11N90C_F109.pdf

The oscillator cannot directly drive the low impedance looking into the FET (2700pF of gate-source capacitance)... so it is not driving the G-S voltage to the 5V level that it (apparently) produces when it looks into the 100 ohm load you have at the input of the IXYS driver.

Try tacking a 0.02uF or 0.047uF capacitor directly between pins 1 and 3 of the IXYS driver before replacing the IXYS driver or redoing the physical layout.

Stu

I put the .047 capacitor between pins 1 and 3 last night but I got nothing for power output.  The oscillator is still working but I get nothing out of the IXYS... it must've gone zorch with all the tweaking.

I'm still waiting for all the new parts to come in, and I'm going to completely re-do the IXYS. 

I'll drill a hole to mount it closer to the FET and reduce the ground lead length by mounting a 90 degree piece of copper directly beneath the IXYS.  It'll then be easier to solder the bypass capacitors directly to the 3rd pin.

And again, I'll use solid 14 gauge wire to supply the 13.8 vdc to the IXYS instead of the thin stuff I have now.

Not relevant to troubleshooting, but I'm also replacing the small ceramic disc capacitors that are in the filter.  I've ordered 1kv micas.

Things all should be in by the weekend, so I'll poster after I get it all done.

Jon

Jon

Some additional information:

If the 5A average FET drain current were an ideal square wave, toggling between 0A and 10A, then the peak-to-peak, fundamental frequency, sinusoidal component of that square wave would be 10A x 4/pi = 12.7A (Yes, the sinusoidal component of a square wave has a peak-to-peak value that is 1.27 x the peak-to-peak value of the square wave). The corresponding  RF output power would be 40.5 watts (with a 2 ohm RF load). The electrical input power would be 13.8V x 5A = 69 watts.

If the 5A average FET drain current were an ideal rectangular wave, on 75% of the time and off 25% of the time, toggling between 0A and 5A/0.75 = 6.67A, then the peak-to-peak fundamental frequency, sinusoidal component of that rectangular wave would be 6.67A x (2/pi) x [sin (0.25 x 2pi)] = 6.67A x (2/pi) x (1) = 4.24A. The corresponding RF output power would be 4.5 watts

If the 5A average FET drain current were an ideal rectangular wave, on 80% of the time and off 20% of the time, toggling between 0A and 5A/0.8 = 6.25A, then the peak-to-peak fundamental frequency, sinusoidal component of that rectangular wave would be 6.25A x (2/pi) x [sin (0.2 x 2pi)] = 6.25A x (2/pi) x (0.95) = 3.784A. The corresponding RF output power would be 3.57 watts.


If the 5A average FET drain current were an ideal square wave + a DC, toggling between 3.5A and 6.5A, then the peak-to-peak fundamental frequency, sinusoidal component of that square wave would be 3A x (4/pi) = 3.82A. The corresponding RF output power would be 3.65 watts.


Stu

So duty cycle makes a huge difference. I guess I should shoot for that perfect square wave.

Jon

...just a thought

Does the IXYS need a switching rail voltage at the input?  13.8vdc on/off?  Steve's class E version shows 12 volts switching input with a 12 volt supply.

Also borrowed material, but I drew this schematic that could go in between the oscillator output and the IXYS input.

Jon

The IXYS driver ic doesn't require a switching stabalisator ic, just a linear one is good enough. The driver current is 100mA to 200mA depending on the gate charge of the mosfet . You can use an linear voltage regulator like an 7812 or 7815.
If the output is low use an another output transformer 1:2 will mostly good enough.

Martin

I re-did everything except the 7806 for the oscillator board.  I unsoldered the 7805 but looked closely at what All Electronics out of California had sent me.  The warehouse guy needs glasses or something because they sent me 7808's instead. 

I did test the new IXYS configuration with the 5 volt regulator in there (before I unsoldered it) and I'm getting 4 watts out.  A slight improvement but nothing near what I should be getting.

I'm going to get some 7806's from DigiKey, but in the meantime, could I put an FT37-43 in between the IXYS and the gate?  Maybe put 4 turns primary to 8 turns secondary to double the voltage driving the FET?

Jon
KA1TDQ

Jon


I don't see the twisted pair transmission line between the oscillator (inverter output bus + inverter ground) and the IXYS chip (input pin 4 + ground pin 3).

As before, if the IXYS chip is working properly, the measured DC voltage between its output pin and ground should be something like 0.5 x 13.8V.

I suspect that you will need an oscilloscope to go much further in troubleshooting this circuit.

Stu

 

Jon

Additional suggestion:

The 100 ohm resistor that is intended to be a load on the output of the oscillator (inverter) is presently connected as follows: output of the oscillator (inverter chip) => pin 4 of the IXYS-chip => 2" of resistor lead length and resistor body=> a point on the shared ground plane => a long path back to the ground of the oscillator (inverter) chip, via the ground plane.

While this seems like a complete circuit that follows the schematic, the large area enclosed by this path can result in a large voltage induced around this path by the magnetic field associated with the large current that is returning to pin 3 (ground) of the IXYS chip via the ground plane. Furthermore, inductance of the portion of this closed path that is shared with the path being taken by the IXYS output ground return current can also introduce large voltages around this path. Remember, all of the IXYS chip output current is flowing into the gate of the FET, and then flowing back from the source of the FET into the IXYS chip's ground pin. This IXYS chip output current is much larger than the current flowing through the output wire (and back) of the oscillator.

I suggest that you tack a 1/4 watt, 100 ohm resistor (physically much smaller than what you have now) between pins 4 and 3 (with leads as short as possible), instead of using the physically large resistor and the wiring approach you have now. The required dissipation capability of this resistor (with a 50% duty cycle 0-to-5V square wave across it) is roughly: 0.5 x 5V x 5V/100 ohms = 0.125 watts. This, combined with the use of a twisted pair between the oscillator and the IXYS chip, will reduce the area enclosed by the round-trip path between the oscillator and the IXYS chip, and will mostly remove any portions of this closed path that are shared with the IXYS output current ground return.

From the IXYS data sheet:

GROUNDING

In order for the design to turn the load off properly, the IXDD414
must be able to drain this 5A of current into an adequate
grounding system. There are three paths for returning current
that need to be considered: Path #1 is between the IXDD414
and it’s load. Path #2 is between the IXDD414 and it’s power
supply. Path #3 is between the IXDD414 and whatever logic
is driving it. All three of these paths should be as low in
resistance and inductance as possible, and thus as short as
practical. In addition, every effort should be made to keep these
three ground paths distinctly separate. Otherwise, (for
instance), the returning ground current from the load may
develop a voltage that would have a detrimental effect on the
logic line driving the IXDD414.

OUTPUT LEAD INDUCTANCE
Of equal importance to Supply Bypassing and Grounding are
issues related to the Output Lead Inductance. Every effort
should be made to keep the leads between the driver and it’s
load as short and wide as possible. If the driver must be placed
farther than 2” from the load, then the output leads should be
treated as transmission lines. In this case, a twisted-pair
should be considered, and the return line of each twisted pair
should be placed as close as possible to the ground pin of the
driver, and connect directly to the ground terminal of the load.

Stu

Ok, that's an easy changeout.  My building will need to be put off for about two months though. I just had a cast put on my soldering arm and hand this morning. It makes typing a real bear too.  But, eh, stuff happens...

Anyway, I'll post another update when I can make it happen.

Jon
KA1TDQ

Jon

Ugh!

Heal quickly!!!

Stu

I did do one easy change that I could do with my right hand. I clipped the Transorbs from the gate of the FET.  Power increased from 3.5 watts to 7 watts. Power also rises as I hold key-down and things warm up. I don't think I'm in danger of exceeding 18 volts on the gate, so I could probably leave this disconnected.

I'm going to change the 100 ohm resistor configuration with twisted pair lead and shorter attachments to the IXYS.  I don't want to do it with my cast on because I'll butcher it for sure. It comes off in 3 weeks, so I guess I can wait.

**One other quick question:

I have the back tab of the IXYS currently isolated from ground via a mica spacer.  From the pictures on the class E website, it looks like they're attached to ground.

---Found the answer:    "The ground terminals of each driver ICs are connected directly to the source bus, and the tab (also ground for the driver ICs) is bolted directly to the heat sink." (per the class E site)

Jon
KA1TDQ

Jon

I thought there was something funny in the schematic regarding the gate TransZorb(R) devices.

From the photo (no stripe on either side), and from the part number in the schematic (1.5KE18CA), I believe that the devices you are using are bidirectional type.

The schematic makes them appear to be unidirectional types. In the schematic, one of them (if it were unidirectional) is forward-biased... providing a conducting path from gate-to-source.

In any event, you should only have one bidirectional device from gate-to-source (not gate-to-a distant ground). The second, parallel device (shown in the schematic as a forward biased Zener diode, which would be the wrong direction if it were a unidirectional type) is not necessary.

Why the presence of one or both of these bi-directional devices would limit the power output (presumably disturbing gate-to-source voltage waveform) is not obvious... but is probably the result of having another "long" path from gate-to-board ground, that has RF voltage being induced into it because of the phenomena I mentioned in earlier posts.

I don't know if the tab of the ISXY device is connected to ground (or any of the other terminals), and I don't see any clarification of this in the specification sheet. You could check with an ohm meter. In any event, I would keep the tab insulated from board/chassis ground.

Stu

I didn't know they were bidirectional. I'll cut one off.  I built it the same way on my other rig too (using analog drive), so I'll cut that one off too.

I've attached the datasheet for the IXYS.  It's confusing though because it says as a note on page 3 to attach the metal tab on "SI" packages to ground.  I think they meant "CI" packages though because SI's are 8 pin DIPs.

Jon

Jon

I would suggest that you not ground the metal tab of the IXYS device.

I would also suggest that, for now, you leave the FET gate-to-source TransSorb(R) overvoltage protection device out. You can add it back in (with short leads, directly between the FET's gate and source) when you have the transmitter working satisfactorily. 

The TransSorb device should have very little effect on the normal behavior of the transmitter... provided its presence is not resulting in excessive RF voltage being induced into the associated wiring loop, or added to a segment of this loop by FET drain current returning to the FET source, via the ground plane.

Stu

Ok, good. That would've required lots of disassembly.

By the way, I did end up getting some 7806's in.  No change in power out.

I've got a plan for the resistor change, twin lead and the 3 ground paths.  I'll also change the TransZorb to G-S leads rather than a distant ground (once I get the transmitter working properly).

Jon

Hi Jon,

Am a bit late to this Thread ...

But regarding the three-terminal voltage regulators;

You could jigger the output voltage of a  7805 regulator up in voltage by adding a silicon diode in the Gnd (center pin of a TO-220 package),  and you will have 5.7 volts,  and so on ...

AND,  as you probably know there is the classic LM-317 adjustable positive three terminal regulator,  where two resistors (or even a pot) determine the output voltage,  within the limits of its specs:

http://en.wikipedia.org/wiki/LM317

This is not directly responsive to the topic of this thread,  I realize ... back to regular programming.

Hope that you will be castoff soon   GL,  72  Vic

One more observation:  I'm using an IXDD614, which appears only to be good to 2 MHz according to the curves on the datasheet.  An IXDD414 goes past 10 MHz.  Maybe it can't switch fast enough?  Nobody seems to carry the IXDD414's anymore though.

Jon

Jon

That could be a limitation... although the rise and fall times for the 614 are actually slightly shorter than the rise and fall times for the 414.

I suggest that you send an E-mail to Steve (WA1QIX) to see if he is still selling 414's from his stash... or if he has a suggestion with respect to the suitability of the 614's for 7MHz operation with a single FET.

Stu

Jon,

I am not an expert on either the IXDD 414 or the 614,  and in a quick look at the datasheets on each,  looks like they are speced to 1 ot 2 Mhz,  at least on the supply current verses frequency.

The rise and fall times on the 614 APPEAR to be greater,  but on the Claire data for the 614,  the specs cover the complete range of temperature,   and on the older IXYS data for the 414,  the temperature is limited to 25 C.   Am not sure that the 614 is really any worse in frequency capability for a given output C in typical use ...

Must be blind,  but cannot find a maximum frequency for a given supply voltage and load C ...   will look further.


FWIW,  Vic

If you look at the Supply Current vs Frequency chart between the two, you can see the difference.  I've attached the datasheets.

Jon

Jon,

Thanks,  have been looking at the data sheets.  I am not certain that the parts are that different.

Need to get to work,  but  the Tr Tf are not that different with other parameters constant twix the two part numbers.

For what ever reason the 614 is speced at a lower PS current mat on the graphic data,  perhaps this is just to cover small surface mount parts that cannot dissipate as much average power ...

The slope of the supply current vs freq is not much different between the 414 and 614,  and bet that your Gate C is not that large,  realize that you are running at about 7.15 Mhz and so on.  More Later.  GL,  Vic

For now, as Stu has suggested, leave the gate transzorbs off !  It just adds capacitance that right now you don't need to deal with.

I think you may need to invest in an oscilloscope  ;)  I am amazed you got this far without one.  You are certainly flying blind.  Without waveforms you really don't know what is going on.

The IXDD614 may or may not work, but the waveform will tell all right away.  Without that, you just don't know.  Things like duty cycle and the like cannot be known without a scope, and I can absolutely tell you that the IXDD414 and probably the IXDD614 *will* change the duty cycle of the input waveform.  I have found the on-time to be longer after going through the IXDD414, meaning it is necessary to over-compensate at the input side in order to get what you want at the output side.  No big deal to do this, but waveform pictures are an absolute necessity.

Regards, Steve

I'll bring my transmitter to work tomorrow and post some waveforms.  As it turns out, the scope here is 60 MHz.

Jon

   Jon, a couple of things to consider...

The scope probe should have a quick rise time, and low capacity load. The probe could be 10:1 or 100:1 but NOT 1;1 ratio. The scope may have a scope probe calibrate output displaying a square wave and an approximate amplitude. The probe if anything other than 1:1 should have a compensating adjustment (trimmer capacitor). Adjust for a nice square wave using the scopes calibrate output signal. It is important to use the ground clip on the probe.

Once done, look across a battery, perhaps a 9V battery, and compare against a DVM. It should be close.

These steps are important because skipping these steps might make any data you measure meaningless.

A sine wave at 7.15 Mhz takes about 140 nano-seconds to complete 1 cycle. So put your scope on 20 ns / division. Set the trigger level at around +2 volts, rising edge trigger, auto mode. On the vertical channel, make sure you are DC coupled, and any bandwidth limit is turned OFF.

Remember that most scopes have the ground clip. These clips work there way back to the 120V plug ground pin. So consider that when you hook it to anything. Sparks could fly.

For fast pulse measurements, the ground clip should be very short, like < 1 inch. A spring around the probe ground ring and offset ~3/8"is commonly used.

Getting good data is difficult. Crap for data though is easy, although meaningless.  :-X

Jim
Wd5JKO

These waveforms were taken at 5 volts/div.  The FET appears to be on for a long duty cycle.  I'll post the oscillator output next.

Also to note:  To be able to see most of the large waveforms, I had to move the ground reference off of center screen. 

Jon

Oscillator output.

It looks to me like everything is working fine, but I need to reduce the duty cycle.  

Steve: By looking at your VFO schematic, it looks like you do that using an inverting HEX buffer and a NAND chip?

Jon

Jon

As a minor aside: You started out to build a "class C" transmitter. What you are really aiming for is something closer to "class D"... where the drain voltage waveform looks something like a square wave.  

Looking at the oscillator output waveform:

It is true that it is not symmetrical with respect to the time spent above its average value versus the time spent below its average value, but it is a lot more symmetrical than the gate waveform and the drain waveform.

One cannot tell, from the photos of the scope screen, what the voltage values are... but I would guess that moving the average value of the oscillator output waveform (i.e. the input to the IXYS chip) down by a fixed amount would improve things quite a bit. I.e. the  oscillator output voltage is above the threshold voltage of the IXYS chip even when it is well below its peak value.

You might be able accomplish this by reducing the supply voltage to the oscillator by placing one or two forward biased 1n4007 diodes in series, between the 5V voltage regulator and the V+ terminal of the oscillator. Each diode will drop the voltage being applied to the V+ terminal by approximately 0.7V.

Another approach that might provide an improvement (possibly in combination with the above) would be to add a capacitor (tack solder it in), in parallel with the existing 100 ohm load resistor on the output of the oscillator. A capacitor with value 220pf would roll off the existing high frequency (harmonic) components (above 7MHz) of the oscillator output waveform. This would make the time-varying part of the input waveform to the IXYS chip more sinusoidal... and that, combined with the average value (adjusted by the method described above) might result in a much better input waveform for the IXYS chip.


Another, more elegant approach would be to add a high speed comparator chip (+ and - analog inputs, TTL output) between the oscillator output (including the 220pF capacitor) and the IXYS input. By using a potentiometer between the 5V regulator output and ground, you could adjust the positive voltage applied to the "-" input of the comparator... and that would allow you to adjust the duty cycle of the 7MHz TTL rectangular wave output of the comparator.

Stu

I actually have a 6 volt regulator in the oscillator right now.  It didn't change the power out from the 5 volt regulator, but I wanted to give it a shot.  I will put the 5 volt regulator back in and then try the diode trick.

I'll pick up a 220 pf cap tonight too.


Jon

  
  I hope my posts concerning my class E testing adds to the thread because getting repeatable data is extremely difficult. Understanding what is necessary at 13.56 Mhz should make dealing with 7.150 Mhz easier. I very much want to see Jon get that 40m rig working as he intends it to be.

   Earlier this week I was debugging a second amplifier test bench. I was nervous about getting repeatable gate drive readings between the same amplifier at two separate test benches. I had the same probes (250 Mhz 100:1), but different model oscilloscopes.

   As I suspected there was about a 20% difference in the peak voltages observed. Then I fine tuned the probe compensation adjust with the scopes built in square wave calibration source. That did it, and the error is nil now.

   These run at 13.56 Mhz where 1 cycle is 74 ns. The FET's are driven with AC drive where the FET gate capacity is part of a high Q resonant circuit. The design is old, so 20 years ago this was pretty much all you could do..at this frequency and power.

   So if one cycle is 74 ns, then 1/2 cycle is 37 ns. These FET's have a VGS Threshold of about 3 volts, and are on pretty hard at 5 volts Vgs. Looking at the gate waveform (scope ground in the middle) we are above +5v for about     25 ns. The drain side is also resonant, but here this is class E. I include the drain side for reference.

Jim
Wd5JKO

Ok, good to see some scope pictures.

The oscillator output should be cleaner, and of course the on time should be adjustable.  Once you can get the input to the driver to look more like a square or trapezoid waveform, with the on-time lower than the off time, your gate waveform should improve quite a bit.  Aside from that, it looks as if the driver IC can drive the gate all ok.

The power output will increase dramatically once the on-time at the gate is less than the off-time.

Regards,  Steve

I didn't do a calibration on the scope before I ran the tests.  I went to work early and just did these quick, few tests.  But, point taken, and these just got me a quick look into what was going on with the transmitter.

Despite the gimpy hand, I re-soldered things but I didn't see much difference.  Actually, when I tried the second diode in line after the 7805, I solder-bridged it and cooked it.

Plan B:

I thought about building a new analog crystal oscillator with a comparator afterward for duty cycle adjustment.  It would take time and money in parts to get it done right.  Instead, I've ordered an 8 MHz DDS VFO that produces square waves and I guess that the duty cycle is adjustable between 1 - 99 %.  It costs $40 from China.

Otherwise, a total oscillator rebuild will need to wait until I get my cast off.  Typing this message alone is taking forever.

Jon

Jon

Hopefully you will heal quickly... which is obviously more important than debugging and completing the transmitter project.

Question: When you measured the "oscillator output" with the scope... was the scope probe connected to a point close to the oscillator output, or was the scope probe connected to a point close to the input of the IXYS driver?

As Jim (WD5JKO) has pointed out, there are some subtleties involved when measuring these waveforms on a transmitter that has very high, time varying currents (peak-to-peak values on the order of 5A, and fast rise and fall times with a 7MHz repetition rate) flowing around long paths. A long path, in this case, is: from the drain pin of the FET => the primary winding of the toroidal transformer => ground (via the B+ bypass capacitor => through the ground plane=> to the source pin of the FET.  I.e. there may be significant voltages induced around the loop formed by the probe and its ground wire, caused by the time vary magnetic fields passing through that loop... and there may be significant voltage drops in segments of the ground return path that are shared by the oscilloscope probe and these large currents. With a periodic waveform, I think these voltages are more of a concern than whether or not the probe is properly "compensated". With this periodic waveform, imperfect compensation of the probe will primarily result in a DC offset of the observed waveform.  In any event, the next time you use an oscilloscope to observe these waveforms... I suggest that you make sure that the ground wire/clip of the probe is connected to a ground point that is as close as possible to the point where the probe tip is connected (or directly to the ground pin on the device that the probe pin is connected to). You can also verify that you are not picking up too much induced voltage (from magnetic fields) by rotating the probe's ground wire to different positions... to see if the observed waveform changes.


Before disassembling the existing transmitter... I suggest that you try a few more, relatively easy things:

a. Install a new 7805 voltage regulator, and leave out the series diodes that I previously suggested. Replace the connection between the existing oscillator's output and the IXYS driver with a balanced twisted pair ... directly connected to the input and ground pins of the IXYS driver. Remove the existing 100 ohm terminating resistor, and replace it with a physically smaller 100 ohm resistor (0.5W or 0.25W is okay), connected with short leads, directly from the IXYS driver input pin to the IXYS driver ground pin. I.e. do not rely on a relatively long ground return path that passes through the ground plane. See if that has a favorable effect on the output power of the transmitter.

b. After observing the effect of a. (above), and in addition to what you have done in a. (above)... tack solder the previously mentioned (in my earlier post) 220pF capacitor (short leads) across the 100 ohm resistor. See if this provides any improvement in the output power.

c. Add in an adjustable, negative DC offset to the output of the oscillator... as follows:

i. On the oscillator board, remove the wire that goes to the input of the IXYS driver from the output bus of the oscillator. Insert a new .01uF capacitor between the output bus of the oscillator and the wire that goes to the input of the IXYS driver. Add a new 1000 ohm 1/2 watt or 1/4 watt resistor from the output bus of the oscillator, to the oscillator board ground.

The result of doing the above will be to "AC-couple" the oscillator output bus to the IYXS driver input... while still providing a 1000 ohm DC path between the oscillator output bus and ground.

This will result in an (approximately) 3V negative offset of the IXYS driver input waveform... versus what it was before.

ii. Connect a 1000 ohm potentiometer between your 5V DC supply and ground. Then connect the wiper of this potentiometer to one side of a 100 ohm series resistor. Then connect the other side of this 100 ohm series resistor to the point on the oscillator board where the new .01uF capacitor and the wire going to the input of the IXYS chip are connected together.

This will allow you to add a positive offset to the AC-coupled oscillator output waveform (i.e. the IXYS driver input waveform)... of between 0V and 2.5V. E.g. with the potentiometer wiper all the way to the + end, the combination of the new 100 ohm series resistor (connected to the wiper) and the existing 100 ohm load (between the IYXS driver input and ground) will form a voltage divider that adds half of the wiper voltage to the IXYS chip input waveform.

By adjusting the added positive  voltage offset, you should be able to shift the input waveform to the IXYS driver back up by enough to cause the IXYS driver to spend a roughly equal amount of time in the "low" output state and the "high" output state.

In the longer run... if you replace the oscillator:

Regardless of whether you use a comparator or not... I suggest that (after your recovery) you use balanced twisted pair to interconnect the new oscillator's output directly to the input of the comparator (if you decide to use one), and to connect the output of the comparator to the IXYS driver.

I put a 7805 back in and ran twisted pair to the IXYS chip.  I also used a 1/4 watt capacitor with much shorter leads to the chip itself.  Before I soldered the new resistor on, I added a 220 pf capacitor across it.  And, I'm still getting roughly 7 watts.

Since then...

I've removed the oscillator board and made a new interface board for the DDS VFO.  It has a 5 volt regulator supply for the VFO and a circuit using a scroteful PNP to switch 13.8 volts to the IXYS chip.  Since the VFO puts out a constant signal, this seemed to be the best way to key the transmitter. 

I will run twisted pair to the TTL logic output of the VFO.  Here's a link for the VFO:

http://www.alibaba.com/product-detail/UDB1008-8Mhz-DDS-Signal-Generator-Board_1591644964.html (http://www.alibaba.com/product-detail/UDB1008-8Mhz-DDS-Signal-Generator-Board_1591644964.html)

I may still hear the oscillator during receive, and I'll cross that bridge later.

Jon
KA1TDQ

Jon

I'm "keeping my fingers crossed" that this will work for you.

As a review of some of your results to date:

1. When you observed the input to the IXYS driver with an oscilloscope, it wasn't half on and half off... but it was off a significant percentage of the time. [Since the use of a balanced twisted pair to connect the oscillator's output bus to the input of the IXYS driver didn't noticeably change the behavior of the circuit, one can assume that the waveform on the output bus of the oscillator is pretty much the same as what was on the input to the IXYS driver]

2. When you observed the FET's gate-to-drain waveform with an oscilloscope, it was high most of the time, with a short duration, high amplitude, downward-going pulse.

The above suggests that the IXYS driver was producing a low output state for a small portion of the time that the input to the IXYS driver was being driven "low". This further suggests that the waveform of the input of the IXYS is at too high a voltage when it is in its "low" state.

I suggest that you look for this problem with the new oscillator. The IXYS chip specification sheet says that it can accommodate an input voltage that is negative (-5V max), so there is no apparent risk in ensuring that the input to the IXYS driver is well below its threshold when you want its output to be low.

Stu

Yeah, it's all about the input to the IXYS chip. I'm still waiting on the slow boat from China for the new oscillator/DDS VFO.

Specs show that output can be a square wave at any duty cycle. I will adjust that for best output power.  Also, output (no load) is 10 volts peak. I will adjust that to just turn on the IXYS (plus a little for margin).

The dc offset is also adjustable to +/-2.5 volts. I guess I would adjust that to ensure that the IXYS is off when it should be. I will need a scope to make all these adjustments.

I've thought about hearing the oscillator during receive. I will put a relay in to kill power to the DDS during receive. From what I've read, the VFO goes right back to where it was when powered off.  I will see...

Come on slow boat!

Jon
Sent from my iPhone while in line at Starbucks

Jon

The DC offset will be particularly handy. I assume that the new oscillator requires both a "+" supply and a "-" supply in order to produce the DC offset. The IXYS should be easy to drive, since it presents a standard TTL load at its input. You want the "high" input to the IXYS driver to be around standard TTL high (i.e. 5V, which is well above the "on" threshold of the IXYS driver). You want the low input to be around 0 Volts (or maybe a little negative if needed to keep any ringing on the oscillator output waveform below the low threshold).

Stu

Sent from my radio room / office at home, where my beautiful wife Margaret limits me to one cup of coffee per day.

The slow boat from China has arrived.

I've mounted the DDS VFO on the front of the transmitter and run twisted pair lead over to the input of the IXYS chip.  I'm using the output port of the DDS rather than the TTL output because I get no power out using TTL. 

The magic number seems to be 44% duty cycle, but I'm only getting 7 watts at that point.  Going down from there reduces power output.  Things get unstable going above that percentage duty cycle.  When I key the transmitter (apply power to the IXYS chip), the transmitter does key, but when I let up there is a higher power output.  This happens with no power applied to the IXYS chip.  To get rid of the output, I need to turn the VFO amplitude pot to zero and start again.

I'll need to take it to work this weekend so that I can throw a scope on it.

Jon
KA1TDQ

I rebuilt the IXYS portion for the 3rd time.  Having the cast off of my hand helps a lot.  This time I ended up using an IXDD414 (just in case) and I also grounded the tab of the chip rather than insulating it from the heat sink.

The instability problem is gone.  However, power output isn't where it should be.  Power creeps up from about 5 watts at 44% duty cycle to 8 watts at 70%. 

With just a few switches, I can switch between my AM rig and this one for the antenna.  And a few switches can put the linear in or out.  With the linear I'm getting 90 watts with this rig.  I'm happy here.  I could troubleshoot more, but, eh...

It sounds nice on the receiver too and the frequency is spot on.  I'm waiting for my electronic keyer to come in the mail and I'll put it on the air.

Jon
KA1TDQ

Jon

Congratulations (cast off, and rig working)!

What is the average drain current when the oscillator output duty cycle is 44% ?

Stu

I don't have an easy way of measuring drain current.  It's on the same terminal connection as the IXYS feed and the power connection for the DDS VFO. 

I can measure total rig current though from the front panel of my 13.8v Astron power supply. 

At 44% Itotal = 2.5 amps = 5 watts
At 70% Itotal = 3.50 amps = 8 watts

I'm guessing the IXYS chip consumes about an amp and the VFO probably does too.  So, for 8 watts output, I'm burning 1.5 amps at 13.8 volts or 20.7 watts.

8 watts / 20.7 watts = 39% efficiency :-)

...of course, these are all guesses.  I would really need to put a current meter in line with the drain.

Jon
KA1TDQ

One final note on this transmitter...

I've been talking with VK3ALK offline about this transmitter and he suggested that the 11N90 was a little too large of a FET for a low power rig.  He suggested replacing it with an IRF510 which has much lower gate capacitance.

I did and got a little more power at 10 watts out.  After that, I decided just to go ahead and bite the bullet and make this a genuine QRP rig.  I dialed down the duty cycle to 44% and that puts the output at just a hair over 5 watts. 

I also added cool blue LED lighting underneath the circuit board as you can see by the picture.  The green LED on the right of the circuit board is rectified RF coming off of the antenna jack.  This gives me a visual indication of actual RF output rather than throwing a wattmeter in-line.

So there it is... Left side of the desk is PW CW, and the right side is KW+ AM.

Jon
KA1TDQ